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<TITLE> 12.11 Performance-Driven Synthesis</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
<P>[ <A HREF="CH12.htm">Chapter start</A> ] [ <A HREF="CH12.a.htm">Previous page</A> ] [ <A HREF="CH12.c.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
<A NAME="pgfId=4866">
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12.11 <A NAME="22485">
</A>
Performance-Driven Synthesis</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=262999">
</A>
Many logic synthesizers allow the use of directives. The <A NAME="marker=295895">
</A>
pseudocomment in the following code directs the logic synthesizer to minimize the delay of an addition:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=263000">
</A>
<B CLASS="Keyword">
module</B>
add_directive (a, b, z); <B CLASS="Keyword">
input</B>
[3:0] a, b; <B CLASS="Keyword">
output</B>
[3:0] z;</P>
<P CLASS="Computer">
<A NAME="pgfId=263001">
</A>
//compass maxDelay 2 ns</P>
<P CLASS="Computer">
<A NAME="pgfId=295892">
</A>
//synopsys and so on.</P>
<P CLASS="Computer">
<A NAME="pgfId=263002">
</A>
assign z = a + b;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=263003">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="Body">
<A NAME="pgfId=360757">
</A>
These directives become complicated when we need to describe complex timing constraints. <A HREF="#31707" CLASS="XRef">
Figure 12.7</A>
(a) shows an example of a more flexible method to measure and specify delay using <SPAN CLASS="Definition">
timing arcs</SPAN>
<A NAME="marker=360761">
</A>
(or timing paths). Suppose we wish to improve the performance of the <A NAME="marker=395373">
</A>
comparator/MUX example from <A HREF="CH12.2.htm#11737" CLASS="XRef">
Section 12.2</A>
. First we define a <SPAN CLASS="Definition">
pathcluster</SPAN>
<A NAME="marker=360765">
</A>
(a group of circuit nodes—see <A HREF="#31707" CLASS="XRef">
Figure 12.7</A>
b). Next, we specify the <SPAN CLASS="Definition">
required time</SPAN>
<A NAME="marker=360769">
</A>
for a signal to reach the output nodes (the <SPAN CLASS="Definition">
end set</SPAN>
<A NAME="marker=360770">
</A>
) as 2 ns. Finally, we specify the <SPAN CLASS="Definition">
arrival time</SPAN>
<A NAME="marker=360771">
</A>
of the signals at all the inputs as 0 ns. We have thus constrained the delay of the comparator/MUX to be 2 ns—measured between any input and any output. The logic-optimization step will simplify the logic network and then map it to a cell library while attempting to meet the timing constraints.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=360777">
</A>
</P>
<DIV>
<IMG SRC="CH12-8.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=360780">
</A>
FIGURE 12.7 <A NAME="31707">
</A>
Timing constraints. (a) A pathcluster. (b) Defining constraints. </P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=360784">
</A>
<A HREF="#11170" CLASS="XRef">
Table 12.11</A>
shows the results of a <A NAME="marker=395374">
</A>
timing-driven logic optimization for the comparator/MUX. Comparing these results with the default optimization results shown in <A HREF="CH12.2.htm#16015" CLASS="XRef">
Table 12.3</A>
reveals that the timing has dramatically improved (critical path delay was 2.43 ns with default optimization settings, and the delay varies between 0.31 ns and 1.64 ns for the timing-driven optimization).</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableTitle">
<A NAME="pgfId=360794">
</A>
TABLE 12.11 <A NAME="11170">
</A>
Timing-driven synthesis reports for the comparator/MUX example of <A HREF="CH12.2.htm#11737" CLASS="XRef">
Section 12.2</A>
.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=360798">
</A>
Command</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=360806">
</A>
Synthesizer output<A HREF="#pgfId=360805" CLASS="footnote">
1</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="ComputerFirst">
<A NAME="pgfId=360808">
</A>
> set pathcluster pc1</P>
<P CLASS="Computer">
<A NAME="pgfId=360809">
</A>
> set requiredTime 2 outp[0] outp[1] outp[2] -pathcluster pc1</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=360810">
</A>
> set arrivalTime 0 * -pathcluster pc1</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=360814">
</A>
> optimize</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=360816">
</A>
Num Gate Count Tot Gate Width Total</P>
<P CLASS="Computer">
<A NAME="pgfId=360817">
</A>
Cell Name Insts Per Cell Count Per Cell Width</P>
<P CLASS="Computer">
<A NAME="pgfId=360818">
</A>
--------- ----- ---------- -------- -------- --------</P>
<P CLASS="Computer">
<A NAME="pgfId=360819">
</A>
an02d1 1 1.3 1.3 12.0 12.0</P>
<P CLASS="Computer">
<A NAME="pgfId=360820">
</A>
in01d0 2 .8 1.5 7.2 14.4</P>
<P CLASS="Computer">
<A NAME="pgfId=360821">
</A>
mx21d1 2 2.2 4.5 21.6 43.2</P>
<P CLASS="Computer">
<A NAME="pgfId=360822">
</A>
nd02d0 2 1.0 2.0 9.6 19.2</P>
<P CLASS="Computer">
<A NAME="pgfId=360823">
</A>
oa03d1 1 1.8 1.8 16.8 16.8</P>
<P CLASS="Computer">
<A NAME="pgfId=360824">
</A>
oa04d1 1 1.3 1.3 12.0 12.0</P>
<P CLASS="Computer">
<A NAME="pgfId=360825">
</A>
--------- ----- ---------- -------- -------- --------</P>
<P CLASS="Computer">
<A NAME="pgfId=360826">
</A>
Totals: 9 12.2 117.6</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=360828">
</A>
> report timing </P>
<P CLASS="Computer">
<A NAME="pgfId=360829">
</A>
-allpaths</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=360831">
</A>
path cluster name: pc1 </P>
<P CLASS="Computer">
<A NAME="pgfId=360832">
</A>
path type: maximum </P>
<P CLASS="Computer">
<A NAME="pgfId=360833">
</A>
----------------------------------------------------------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=360834">
</A>
end node current required slack </P>
<P CLASS="Computer">
<A NAME="pgfId=360835">
</A>
----------------------------------------------------------------------</P>
<P CLASS="Computer">
<A NAME="pgfId=360836">
</A>
outp[1] 1.64 2.00 .36 MET </P>
<P CLASS="Computer">
<A NAME="pgfId=360837">
</A>
outp[0] 1.64 2.00 .36 MET </P>
<P CLASS="Computer">
<A NAME="pgfId=360838">
</A>
outp[2] .31 2.00 1.69 MET </P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=296109">
</A>
<A HREF="#32025" CLASS="XRef">
Figure 12.8</A>
shows that timing-driven optimization and the subsequent mapping have simplified the logic considerably. For example, the logic for <SPAN CLASS="BodyComputer">
outp[2]</SPAN>
has been reduced to a two-input AND gate. Using <SPAN CLASS="BodyComputer">
sis</SPAN>
reveals how optimization works in this case. <A HREF="#24751" CLASS="XRef">
Table 12.12</A>
shows the equations for the intermediate signal <SPAN CLASS="BodyComputer">
sel</SPAN>
and the three comparator/MUX outputs in the BLIF. Thus, for example, the following line of the BLIF code in <A HREF="#24751" CLASS="XRef">
Table 12.12</A>
(the first line following <SPAN CLASS="BodyComputer">
.names a0 b0 a1 b1 a2 b2 sel</SPAN>
) includes the term <SPAN CLASS="BodyComputer">
a0·b0'·a1'·b1'·a2'·b2'</SPAN>
in the equation for <SPAN CLASS="BodyComputer">
sel</SPAN>
:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=296116">
</A>
100000 1</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=263092">
</A>
There are six similar lines that describe the six other product terms for <SPAN CLASS="BodyComputer">
sel</SPAN>
. These seven product terms form a cover for <SPAN CLASS="BodyComputer">
sel</SPAN>
in the Karnaugh maps of <A HREF="CH12.3.htm#29776" CLASS="XRef">
Figure 12.5</A>
. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=263069">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=360756">
</A>
`timescale 1ns / 10ps</P>
<P CLASS="Computer">
<A NAME="pgfId=263071">
</A>
<B CLASS="Keyword">
module</B>
comp_mux_o (a, b, outp);</P>
<P CLASS="Computer">
<A NAME="pgfId=263072">
</A>
<B CLASS="Keyword">
input</B>
[2:0] a; <B CLASS="Keyword">
input</B>
[2:0] b;</P>
<P CLASS="Computer">
<A NAME="pgfId=263073">
</A>
<B CLASS="Keyword">
output</B>
[2:0] outp;</P>
<P CLASS="Computer">
<A NAME="pgfId=263074">
</A>
<B CLASS="Keyword">
supply1</B>
VDD; <B CLASS="Keyword">
supply0</B>
VSS;</P>
<P CLASS="Computer">
<A NAME="pgfId=263075">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=263076">
</A>
mx21d1 B1_i1 (.I0(a[0]), .I1(b[0]), .S(B1_i6_ZN), .Z(outp[0]));</P>
<P CLASS="Computer">
<A NAME="pgfId=263077">
</A>
oa03d1 B1_i2 (.A1(B1_i9_ZN), .A2(a[2]), .B1(a[0]), .B2(a[1]), .C(B1_i4_ZN), .ZN(B1_i2_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=263078">
</A>
nd02d0 B1_i3 (.A1(a[1]), .A2(a[0]), .ZN(B1_i3_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=263079">
</A>
nd02d0 B1_i4 (.A1(b[1]), .A2(B1_i3_ZN), .ZN(B1_i4_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=263080">
</A>
mx21d1 B1_i5 (.I0(a[1]), .I1(b[1]), .S(B1_i6_ZN), .Z(outp[1]));</P>
<P CLASS="Computer">
<A NAME="pgfId=263081">
</A>
oa04d1 B1_i6 (.A1(b[2]), .A2(B1_i7_ZN), .B(B1_i2_ZN), .ZN(B1_i6_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=263082">
</A>
in01d0 B1_i7 (.I(a[2]), .ZN(B1_i7_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=263083">
</A>
an02d1 B1_i8 (.A1(b[2]), .A2(a[2]), .Z(outp[2]));</P>
<P CLASS="Computer">
<A NAME="pgfId=263084">
</A>
in01d0 B1_i9 (.I(b[2]), .ZN(B1_i9_ZN));</P>
<P CLASS="Computer">
<A NAME="pgfId=263085">
</A>
</P>
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