ch12.3.htm

来自「介绍asci设计的一本书」· HTM 代码 · 共 472 行 · 第 1/2 页

 </A>
 step builds a generic network from the optimized logic network. The generic network is usually simple NAND gates (<SPAN CLASS="BodyComputer">
sis</SPAN>
 uses either AND, or NOR gates, or both). This generic network is in a technology-independent form. To build this generic network involves creating intermediate nodes. The program <SPAN CLASS="BodyComputer">
sis</SPAN>
 labels these intermediate nodes<SPAN CLASS="BodyComputer">
 [n]</SPAN>
, starting at <SPAN CLASS="BodyComputer">
n  =  100</SPAN>
.</P>
<P CLASS="ComputerNmbr">
<A NAME="pgfId=261348">
 </A>
<A NAME="11068">
 </A>
sel = [100] * [101] * [102] ;[12.5]</P>
<P CLASS="Computer">
<A NAME="pgfId=261353">
 </A>
[100] = !( !a2 * [103] );</P>
<P CLASS="Computer">
<A NAME="pgfId=261358">
 </A>
[101] = !( b2 * [103] );</P>
<P CLASS="Computer">
<A NAME="pgfId=261359">
 </A>
[102] = !( !a2 * b2 );</P>
<P CLASS="Computer">
<A NAME="pgfId=261365">
 </A>
[103] = !( [104] * [105] * [106] );</P>
<P CLASS="Computer">
<A NAME="pgfId=261406">
 </A>
[104] = !( !a1 * b1 );</P>
<P CLASS="Computer">
<A NAME="pgfId=261367">
 </A>
[105] = !( b0 * [107] );</P>
<P CLASS="Computer">
<A NAME="pgfId=261398">
 </A>
[106] = !( a0' * [107] );</P>
<P CLASS="Computer">
<A NAME="pgfId=261399">
 </A>
[107] = !( a1 * !b1 );</P>
<P CLASS="ComputerNmbr">
<A NAME="pgfId=261442">
 </A>
<A NAME="25237">
 </A>
outp2 = !( [108] * [109] );[12.6]</P>
<P CLASS="Computer">
<A NAME="pgfId=261452">
 </A>
[108] = !( a2 * !sel );</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=261453">
 </A>
[109] = !( sel * b2 );</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=172178">
 </A>
There are two other sets of equations, similar to Eq.&nbsp;<A HREF="#25237" CLASS="XRef">
12.6</A>
, for <SPAN CLASS="BodyComputer">
outp1</SPAN>
 and <SPAN CLASS="BodyComputer">
outp0</SPAN>
. Notice the polarity of the <SPAN CLASS="BodyComputer">
sel</SPAN>
 signal in Eq.&nbsp;<A HREF="#11068" CLASS="XRef">
12.5</A>
 is correct and represents an AND gate (a consequence of labeling <SPAN CLASS="BodyComputer">
sel</SPAN>
 as the MUX select input in <A HREF="CH12.1.htm#40122" CLASS="XRef">
Table&nbsp;12.1</A>
).</P>
<P CLASS="Body">
<A NAME="pgfId=261484">
 </A>
Next, the <SPAN CLASS="Definition">
technology-mapping</SPAN>
<A NAME="marker=284251">
 </A>
 step (or <SPAN CLASS="Definition">
logic-mapping</SPAN>
<A NAME="marker=284246">
 </A>
 step) implements the technology-independent network by matching pieces of the network with the logic cells that are available in a technology-dependent cell library (an FPGA or standard-cell library, for example). While performing the logic mapping, the algorithms attempt to minimize area (the default constraint) while meeting any other user constraints (timing or power constraints, for example).</P>
<P CLASS="Body">
<A NAME="pgfId=228934">
 </A>
Working backward from the outputs the logic mapper recognizes that each of the three output nodes (<SPAN CLASS="BodyComputer">
outp2</SPAN>
, <SPAN CLASS="BodyComputer">
outp1</SPAN>
, and <SPAN CLASS="BodyComputer">
outp0</SPAN>
) may be mapped to a MUX. (We are using the term &#8220;node mapping to a logic cell&#8221; rather loosely here&#8212;an exact parallel is a compiler mapping patterns of source code to object code.) Here is the equation that shows the mapping for <SPAN CLASS="BodyComputer">
outp2</SPAN>
:</P>
<P CLASS="ComputerNmbr">
<A NAME="pgfId=261547">
 </A>
<A NAME="37384">
 </A>
outp2 = MUX(a, b, c) = ac + b!c[12.7]</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=261647">
 </A>
a&nbsp;=&nbsp;b2&nbsp;; b&nbsp;=&nbsp;a2&nbsp;; c&nbsp;=&nbsp;sel</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=261532">
 </A>
The equations for <SPAN CLASS="BodyComputer">
outp1</SPAN>
 and <SPAN CLASS="BodyComputer">
outp0</SPAN>
 are similar.</P>
<P CLASS="Body">
<A NAME="pgfId=284263">
 </A>
The node <SPAN CLASS="BodyComputer">
sel</SPAN>
 can be mapped to the three-input majority function as follows:</P>
<P CLASS="ComputerNmbr">
<A NAME="pgfId=261497">
 </A>
sel =<SPAN CLASS="BodyComputer">
 MAJ3(w, x, y) = !(wx + wy + xy)</SPAN>
[12.8]</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=261498">
 </A>
<SPAN CLASS="BodyComputer">
w&nbsp;=&nbsp;!a2&nbsp;; x&nbsp;=&nbsp;b2&nbsp;; y = [103]&nbsp;; </SPAN>
</P>
<P CLASS="Body">
<A NAME="pgfId=10641">
 </A>
Next node <SPAN CLASS="BodyComputer">
[103] </SPAN>
is mapped to an OAI22 cell,</P>
<P CLASS="ComputerNmbr">
<A NAME="pgfId=245464">
 </A>
<SPAN CLASS="BodyComputer">
[103] = OAI22(w, x, y, z) = ! ((w&nbsp;+&nbsp;x)(y&nbsp;+&nbsp;z)) = (!w!x&nbsp;+&nbsp;!y!z)</SPAN>
<A NAME="20673">
 </A>
[12.9]</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=245465">
 </A>
<SPAN CLASS="BodyComputer">
w&nbsp;=&nbsp;a0&nbsp;; x&nbsp;=&nbsp;a1&nbsp;; y = !b1 z&nbsp;=&nbsp;[107] ; </SPAN>
</P>
<P CLASS="Body">
<A NAME="pgfId=245469">
 </A>
Finally, node <SPAN CLASS="BodyComputer">
[107] </SPAN>
is mapped to a two-input NOR with one inverted input,</P>
<P CLASS="ComputerOneLNmbr">
<A NAME="pgfId=10934">
 </A>
<SPAN CLASS="BodyComputer">
[107] = !(b1 + !a1) ;</SPAN>
<A NAME="38629">
 </A>
[12.10]</P>
<P CLASS="Body">
<A NAME="pgfId=284273">
 </A>
Putting Equations <A HREF="#37384" CLASS="XRef">
12.7</A>
&#8211;<A HREF="#38629" CLASS="XRef">
12.10</A>
 together describes the following optimized logic network (corresponding to the structural netlist and schematic shown in <A HREF="CH12.2.htm#16015" CLASS="XRef">
Figure&nbsp;12.3</A>
):</P>
<P CLASS="ComputerOneLNmbr">
<A NAME="pgfId=284278">
 </A>
sel = !((( !a0 * !(a1&amp;!b1) | (b1*!a1) ) * (!a2|b2) ) | (!a2*b2)) ;[12.11]</P>
<P CLASS="Computer">
<A NAME="pgfId=261559">
 </A>
outp2 = !sel * a2 | sel * b2;</P>
<P CLASS="Computer">
<A NAME="pgfId=261560">
 </A>
outp1 = !sel * a1 | sel * b1;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=261561">
 </A>
outp0 = !sel * a0 | sel * b0;</P>
<P CLASS="Body">
<A NAME="pgfId=284281">
 </A>
The comparator/MUX example illustrates how logic synthesis takes the behavioral model (the HDL input) and, in a series of steps, converts this to a structural model describing the connections of logic cells from a cell library. </P>
<P CLASS="Body">
<A NAME="pgfId=307056">
 </A>
When we write a C&nbsp;program we almost never think of the object code that will result. When we write HDL it is always necessary to consider the hardware. In C there is not much difference between <SPAN CLASS="BodyComputer">
i*j</SPAN>
 and <SPAN CLASS="BodyComputer">
i/j</SPAN>
. In an HDL, if <SPAN CLASS="BodyComputer">
i</SPAN>
 and <SPAN CLASS="BodyComputer">
j</SPAN>
 are 32-bit numbers, <SPAN CLASS="BodyComputer">
i*j</SPAN>
 will take up a large amount of silicon. If <SPAN CLASS="BodyComputer">
j</SPAN>
 is a constant, equal to 2, then <SPAN CLASS="BodyComputer">
i*j</SPAN>
 take up hardly any space at all. Most logic synthesizers cannot even produce logic to implement <SPAN CLASS="BodyComputer">
i/j</SPAN>
. In the following sections we shall examine the Verilog and VHDL languages as a way to communicate with a logic synthesizer. Using one of these HDLs we have to tell the logic synthesizer what hardware we want&#8212;we <SPAN CLASS="Definition">
imply</SPAN>
<A NAME="marker=223200">
 </A>
 A. The logic synthesizer then has to figure out what we want&#8212;it has to <SPAN CLASS="Definition">
infer</SPAN>
<A NAME="marker=223202">
 </A>
 B. The problem is making sure that we write the HDL code such that A  =  B. As will become apparent, the more clearly we imply what we mean, the easier the logic synthesizer can infer what we want.</P>
<HR><P>[&nbsp;<A HREF="CH12.htm">Chapter&nbsp;start</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH12.2.htm">Previous&nbsp;page</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH12.4.htm">Next&nbsp;page</A>&nbsp;]</P></BODY>

<!--#include file="Copyright.html"--><!--#include file="footer.html"-->