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<TITLE> 12.3 Inside a Logic Synthesizer </TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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12.3 <B CLASS="Keyword">
</B>
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Inside a Logic Synthesizer </H1>
<P CLASS="BodyAfterHead">
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The logic synthesizer parses the Verilog of <A HREF="CH12.1.htm#40122" CLASS="XRef">
Figure 12.1</A>
and builds an internal data structure (usually a graph represented by linked lists). Such an abstract representation is not easy to visualize, so we shall use pictures instead. The first <SPAN CLASS="Definition">
Karnaugh map</SPAN>
<A NAME="marker=262732">
</A>
in <A HREF="#29776" CLASS="XRef">
Figure 12.5</A>
(a) is a picture that represents the <SPAN CLASS="BodyComputer">
sel</SPAN>
signal (labeled as the input to the three MUXes in the schematic of <A HREF="CH12.1.htm#40122" CLASS="XRef">
Figure 12.1</A>
) for the case when the inputs are such that <SPAN CLASS="BodyComputer">
a[2]b[2] = 00</SPAN>
. The signal <SPAN CLASS="BodyComputer">
sel</SPAN>
is responsible for steering the smallest input, <SPAN CLASS="BodyComputer">
a</SPAN>
or <SPAN CLASS="BodyComputer">
b</SPAN>
, to the output of the comparator/MUX. We insert a <SPAN CLASS="BodyComputer">
'1'</SPAN>
in the Karnaugh map (which will select the input <SPAN CLASS="BodyComputer">
b</SPAN>
to be the output) whenever <SPAN CLASS="BodyComputer">
b</SPAN>
is smaller than <SPAN CLASS="BodyComputer">
a</SPAN>
. When <SPAN CLASS="BodyComputer">
a = b</SPAN>
we do not care whether we select <SPAN CLASS="BodyComputer">
a</SPAN>
or <SPAN CLASS="BodyComputer">
b</SPAN>
(since <SPAN CLASS="BodyComputer">
a</SPAN>
and <SPAN CLASS="BodyComputer">
b</SPAN>
are equal), so we insert an <SPAN CLASS="BodyComputer">
'x'</SPAN>
, a <A NAME="marker=284018">
</A>
<A NAME="marker=284019">
</A>
don’t care logic value, in the Karnaugh map of <A HREF="#29776" CLASS="XRef">
Figure 12.5</A>
(a). There are four Karnaugh maps for the signal <SPAN CLASS="BodyComputer">
sel</SPAN>
, one each for the values <SPAN CLASS="BodyComputer">
a[2]b[2] = 00</SPAN>
, <SPAN CLASS="BodyComputer">
a[2]b[2] = 01</SPAN>
, <SPAN CLASS="BodyComputer">
a[2]b[2] = 10</SPAN>
, and <SPAN CLASS="BodyComputer">
a[2]b[2] = 11</SPAN>
.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
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<IMG SRC="CH12-5.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=71240">
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FIGURE 12.5 <A NAME="29776">
</A>
Logic maps for the comparator/MUX. (a) If the input <SPAN CLASS="BodyComputer">
b</SPAN>
is less than <SPAN CLASS="BodyComputer">
a</SPAN>
, then <SPAN CLASS="BodyComputer">
sel</SPAN>
is <SPAN CLASS="BodyComputer">
'1'</SPAN>
. If <SPAN CLASS="BodyComputer">
a = b</SPAN>
, then <SPAN CLASS="BodyComputer">
sel = 'x'</SPAN>
(don’t care). (b) A cover for <SPAN CLASS="BodyComputer">
sel</SPAN>
.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=261176">
</A>
Next, <SPAN CLASS="Definition">
logic minimization</SPAN>
<A NAME="marker=326871">
</A>
tries to find a minimum <SPAN CLASS="Definition">
cover</SPAN>
<A NAME="marker=262731">
</A>
for the Karnaugh maps—the smallest number of the largest possible circles to cover all the <SPAN CLASS="BodyComputer">
'1'</SPAN>
s. One possible cover is shown in <A HREF="#29776" CLASS="XRef">
Figure 12.5</A>
(b).</P>
<P CLASS="Body">
<A NAME="pgfId=326900">
</A>
In order to understand the steps that follow we shall use some notation from the <A NAME="marker=326901">
</A>
<SPAN CLASS="Definition">
Berkeley Logic Interchange Format</SPAN>
(<A NAME="marker=326902">
</A>
<SPAN CLASS="Definition">
BLIF</SPAN>
) and from the Berkeley tools <SPAN CLASS="BodyComputer">
misII</SPAN>
<A NAME="marker=326956">
</A>
and <SPAN CLASS="BodyComputer">
sis</SPAN>
<A NAME="marker=326957">
</A>
. We shall use the logic operators (in decreasing order of their precedence): <SPAN CLASS="BodyComputer">
'!'</SPAN>
(negation), <SPAN CLASS="BodyComputer">
'*'</SPAN>
(AND), <SPAN CLASS="BodyComputer">
'+'</SPAN>
(OR). We shall also abbreviate Verilog signal names; writing <SPAN CLASS="BodyComputer">
a[2]</SPAN>
as <SPAN CLASS="BodyComputer">
a2</SPAN>
, for example. We can write equations for <SPAN CLASS="BodyComputer">
sel</SPAN>
and the output signals of the comparator/MUX in the format that is produced by <SPAN CLASS="BodyComputer">
sis</SPAN>
, as follows (this is the same format as input file for the Berkeley tool <SPAN CLASS="BodyComputer">
eqntott</SPAN>
<A NAME="marker=326906">
</A>
):</P>
<P CLASS="ComputerOneLNmbr">
<A NAME="pgfId=245435">
</A>
<A NAME="17403">
</A>
sel = a1*!b1*!b2 + a0*!b1*!b2 + a0*a1*!b2 + a1*!b1*a2 + a0*!b1*a2 + a0*a1*a2 + a2*!b2;[12.1]</P>
<P CLASS="ComputerNmbr">
<A NAME="pgfId=261143">
</A>
outp2 = !sel*a2 + sel*b2;[12.2]</P>
<P CLASS="ComputerNmbr">
<A NAME="pgfId=261144">
</A>
outp1 = !sel*a1 + sel*b1;[12.3]</P>
<P CLASS="ComputerOneLNmbr">
<A NAME="pgfId=261145">
</A>
<A NAME="32618">
</A>
outp0 = !sel*a0 + sel*b0;[12.4]</P>
<P CLASS="Body">
<A NAME="pgfId=261300">
</A>
Equations <A HREF="#17403" CLASS="XRef">
12.1</A>
–<A HREF="#32618" CLASS="XRef">
12.4</A>
describe the <SPAN CLASS="Definition">
synthesized network</SPAN>
<A NAME="marker=313562">
</A>
. There are seven product terms in Eq. <A HREF="#17403" CLASS="XRef">
12.1</A>
—the logic equation for <SPAN CLASS="BodyComputer">
sel</SPAN>
(numbered and labeled in the drawing of the cover for <SPAN CLASS="BodyComputer">
sel</SPAN>
in <A HREF="#29776" CLASS="XRef">
Figure 12.5</A>
). We shall keep track of the <SPAN CLASS="BodyComputer">
sel </SPAN>
signal separately even though this is not exactly the way the logic synthesizer works—the synthesizer looks at all the signals at once.</P>
<P CLASS="Body">
<A NAME="pgfId=284106">
</A>
<SPAN CLASS="Definition">
Logic optimization</SPAN>
<A NAME="marker=326870">
</A>
uses a series of factoring, substitution, and elimination steps to simplify the equations that represent the synthesized network. A simple analogy would be the simplification of arithmetic expressions. Thus, for example, we can simplify 189 / 315 to 0.6 by factoring the top and bottom lines and eliminating common factors as follows: (3 <SPAN CLASS="Symbol">
¥</SPAN>
7 <SPAN CLASS="Symbol">
¥</SPAN>
9) / (5 <SPAN CLASS="Symbol">
¥</SPAN>
7 <SPAN CLASS="Symbol">
¥</SPAN>
9) = 3 / 5. Boolean algebra is more complicated than ordinary algebra. To make logic optimization tractable, most tools use algorithms based on algebraic factors rather than Boolean factors. </P>
<P CLASS="Body">
<A NAME="pgfId=307235">
</A>
Logic optimization attempts to simplify the equations in the hope that this will also minimize area and maximize speed. In the synthesis results presented in <A HREF="CH12.2.htm#23004" CLASS="XRef">
Table 12.3</A>
, we accepted the default optimization settings without setting any constraints. Thus only a minimum amount of logic optimization is attempted that did not alter the synthesized network in this case.</P>
<P CLASS="Body">
<A NAME="pgfId=261194">
</A>
The <SPAN CLASS="Definition">
technology-decomposition</SPAN>
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