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<H1 CLASS="Heading1">
<A NAME="pgfId=297434">
</A>
12.10 <A NAME="12259">
</A>
The Engine Controller</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=297441">
</A>
This section returns to the <A NAME="marker=395370">
</A>
example from Section 10.16, “An Engine Controller.” This ASIC gathers sampled temperature measurements from sensors, converts the temperature values from Fahrenheit to Centigrade, averages them, and stores them in a <A NAME="marker=395369">
</A>
FIFO before passing the values to a microprocessor on a three-state bus. We receive the following message from the logic synthesizer when we use the FIFO-controller code shown in Table 10.25:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=266692">
</A>
Warning: Made latches to store values on: net d(4), d(5), d(6), d(7), d(8), d(9), d(10), d(11), in module fifo_control</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=266528">
</A>
This message often indicates that we forgot to initialize a variable. </P>
<P CLASS="Body">
<A NAME="pgfId=333876">
</A>
Here is the part of the code from Table 10.25 that assigns to the vector <SPAN CLASS="BodyComputer">
D</SPAN>
(the error message for <SPAN CLASS="BodyComputer">
d</SPAN>
is in lowercase—remember VHDL is case insensitive):</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=266695">
</A>
<B CLASS="Keyword">
case</B>
sel <B CLASS="Keyword">
is</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=266529">
</A>
<B CLASS="Keyword">
when</B>
"01" => D <= D_1 <B CLASS="Keyword">
after</B>
TPD; r1 <= '1' <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="Computer">
<A NAME="pgfId=266530">
</A>
<B CLASS="Keyword">
when</B>
"10" => D <= D_2 <B CLASS="Keyword">
after</B>
TPD; r2 <= '1' <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="Computer">
<A NAME="pgfId=266531">
</A>
<B CLASS="Keyword">
when</B>
"00" => D(3) <= f1 <B CLASS="Keyword">
after</B>
TPD; D(2) <= f2 <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="Computer">
<A NAME="pgfId=266532">
</A>
D(1) <= e1 <B CLASS="Keyword">
after</B>
TPD; D(0) <= e2 <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="Computer">
<A NAME="pgfId=266533">
</A>
<B CLASS="Keyword">
when</B>
<B CLASS="Keyword">
others</B>
=> D <= "ZZZZZZZZZZZZ" <B CLASS="Keyword">
after</B>
TPD; </P>
<P CLASS="ComputerLast">
<A NAME="pgfId=266842">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
case</B>
;</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=266843">
</A>
When <SPAN CLASS="BodyComputer">
sel = "00"</SPAN>
, there is no assignment to <SPAN CLASS="BodyComputer">
D(4)</SPAN>
through <SPAN CLASS="BodyComputer">
D(11)</SPAN>
. This did not matter in the simulation, but to reproduce the exact behavior of the HDL code the logic synthesizer generates latches to remember the values of <SPAN CLASS="BodyComputer">
D(4)</SPAN>
through <SPAN CLASS="BodyComputer">
D(11)</SPAN>
.</P>
<P CLASS="Body">
<A NAME="pgfId=333877">
</A>
This problem may be corrected by replacing the <SPAN CLASS="BodyComputer">
"00"</SPAN>
choice with the following:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=266543">
</A>
<B CLASS="Keyword">
when</B>
"00" => D(3) <= f1 <B CLASS="Keyword">
after</B>
TPD; D(2) <= f2 <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="Computer">
<A NAME="pgfId=266544">
</A>
D(1) <= e1 <B CLASS="Keyword">
after</B>
TPD; D(0) <= e2 <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=266556">
</A>
D(11 <B CLASS="Keyword">
downto</B>
4) <= "ZZZZZZZZ" <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="Body">
<A NAME="pgfId=297315">
</A>
The synthesizer recognizes the assignment of the high-impedance logic value <SPAN CLASS="BodyComputer">
'Z'</SPAN>
to a signal as an indication to implement a three-state buffer. However, there are two kinds of three-state buffers: core logic three-state buffers and three-state I/O cells. We want a three-state I/O cell containing a bonding pad and not a three-state buffer located in the core logic. If we synthesize the code in Table 10.25, we get a three-state buffer in the core. <A HREF="#33441" CLASS="XRef">
Table 12.9</A>
shows the modified code that will synthesize to three-state I/O cells. The signal OE_b drives the output enable (active-low) of the three-state buffers. <A HREF="#20721" CLASS="XRef">
Table 12.10</A>
shows the top-level code including all the I/O cells. </P>
<TABLE>
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="TableTitle">
<A NAME="pgfId=297451">
</A>
TABLE 12.9 <A NAME="33441">
</A>
A modified version of the FIFO controller to drive three-state I/O cells.</P>
</TH>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=297453">
</A>
<B CLASS="Keyword">
library</B>
IEEE;<B CLASS="Keyword">
use</B>
IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
;<B CLASS="Keyword">
use</B>
IEEE.NUMERIC_STD.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297454">
</A>
<B CLASS="Keyword">
entity</B>
fifo_control <B CLASS="Keyword">
is</B>
<B CLASS="Keyword">
generic </B>
TPD:TIME := 1 ns;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297455">
</A>
<B CLASS="Keyword">
port</B>
(D_1, D_2: <B CLASS="Keyword">
in</B>
UNSIGNED(11 <B CLASS="Keyword">
downto</B>
0); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297456">
</A>
sel : <B CLASS="Keyword">
in</B>
UNSIGNED(1 <B CLASS="Keyword">
downto</B>
0) ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297457">
</A>
read , f1, f2, e1, e2 : <B CLASS="Keyword">
in</B>
STD_LOGIC;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297458">
</A>
r1, r2, w12:<B CLASS="Keyword">
out</B>
STD_LOGIC; D: <B CLASS="Keyword">
out</B>
UNSIGNED(11 downto 0);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297459">
</A>
OE:<B CLASS="Keyword">
out</B>
STD_LOGIC ) ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297460">
</A>
<B CLASS="Keyword">
end</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297461">
</A>
<B CLASS="Keyword">
architecture</B>
rtl <B CLASS="Keyword">
of</B>
fifo_control <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297462">
</A>
<B CLASS="Keyword">
begin</B>
<B CLASS="Keyword">
process </B>
(read, sel, D_1, D_2, f1, f2, e1, e2)</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297463">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297464">
</A>
r1 <= '0' <B CLASS="Keyword">
after</B>
TPD; r2 <= '0' <B CLASS="Keyword">
after</B>
TPD; OE_b <= '0' <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297465">
</A>
<B CLASS="Keyword">
if</B>
(read = '1') <B CLASS="Keyword">
then</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297466">
</A>
w12 <= '0' <B CLASS="Keyword">
after</B>
TPD; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297467">
</A>
<B CLASS="Keyword">
case</B>
sel <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297468">
</A>
<B CLASS="Keyword">
when</B>
"01" => D <= D_1 <B CLASS="Keyword">
after</B>
TPD; r1 <= '1' <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297469">
</A>
<B CLASS="Keyword">
when</B>
"10" => D <= D_2 <B CLASS="Keyword">
after</B>
TPD; r2 <= '1' <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297470">
</A>
<B CLASS="Keyword">
when</B>
"00" => D(3) <= f1 <B CLASS="Keyword">
after</B>
TPD; D(2) <= f2 <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297471">
</A>
D(1) <= e1 <B CLASS="Keyword">
after</B>
TPD; D(0) <= e2 <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297472">
</A>
D(11 <B CLASS="Keyword">
downto</B>
4) <= "00000000" <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297473">
</A>
<B CLASS="Keyword">
when</B>
<B CLASS="Keyword">
others</B>
=> OE_b <= '1' <B CLASS="Keyword">
after</B>
TPD; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297474">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
case</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297475">
</A>
<B CLASS="Keyword">
elsif</B>
(read = '0') <B CLASS="Keyword">
then</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297476">
</A>
OE_b <= '0' <B CLASS="Keyword">
after</B>
TPD; w12 <= '1' <B CLASS="Keyword">
after</B>
TPD;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297477">
</A>
<B CLASS="Keyword">
else</B>
OE_b <= '0' <B CLASS="Keyword">
after</B>
TPD; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297478">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=297479">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=297480">
</A>
<B CLASS="Keyword">
end</B>
rtl;</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TH ROWSPAN="1" COLSPAN="1">
<P CLASS="TableTitle">
<A NAME="pgfId=297331">
</A>
TABLE 12.10 <A NAME="20721">
</A>
The top-level VHDL code for the engine controller ASIC.</P>
</TH>
</TR>
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