ch12.6.htm
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<P CLASS="Computer">
<A NAME="pgfId=287512">
</A>
RST : <B CLASS="Keyword">
in</B>
STD_LOGIC );</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=287503">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
component</B>
;</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=287519">
</A>
Now you have enough information to be able to instantiate both logic cells from a cell library and standard components. The following model illustrates instantiation:</P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=4190">
</A>
<B CLASS="Keyword">
library</B>
IEEE, COMPASS_LIB; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=287213">
</A>
<B CLASS="Keyword">
use</B>
IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
;<B CLASS="Keyword">
use</B>
COMPASS_LIB.STDCOMP.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=287212">
</A>
<B CLASS="Keyword">
entity</B>
Ripple_4 <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4192">
</A>
<A NAME="27019">
</A>
<B CLASS="Keyword">
port</B>
(Trig, Reset: STD_LOGIC; QN0_5x: <B CLASS="Keyword">
out</B>
STD_LOGIC;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4198">
</A>
<A NAME="22357">
</A>
Q : <B CLASS="Keyword">
inout </B>
STD_LOGIC_VECTOR(0 <B CLASS="Keyword">
to</B>
3));</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4200">
</A>
<B CLASS="Keyword">
end</B>
Ripple_4;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4204">
</A>
<B CLASS="Keyword">
architecture</B>
structure <B CLASS="Keyword">
of</B>
Ripple_4 <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4206">
</A>
<A NAME="26457">
</A>
<B CLASS="Keyword">
signal</B>
QN : STD_LOGIC_VECTOR(0 <B CLASS="Keyword">
to</B>
3); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=287475">
</A>
<B CLASS="Keyword">
component</B>
in01d1</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=287476">
</A>
<B CLASS="Keyword">
port</B>
( I : in Std_Logic; ZN : out Std_Logic ); <B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
component</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=287485">
</A>
<B CLASS="Keyword">
component</B>
in01d5</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=287486">
</A>
<B CLASS="Keyword">
port</B>
( I : in Std_Logic; ZN : out Std_Logic ); <B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
component</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=287477">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4210">
</A>
<A NAME="33425">
</A>
--compass dontTouch inv5x -- synopsys dont_touch etc.</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=264127">
</A>
-- Named association for hand-instantiated library cells:</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4212">
</A>
<A NAME="29936">
</A>
inv5x: IN01D5 <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
( I=>Q(0), ZN=>QN0_5x );</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4216">
</A>
inv0 : IN01D1 <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
( I=>Q(0), ZN=>QN(0) ); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4218">
</A>
inv1 : IN01D1 <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
( I=>Q(1), ZN=>QN(1) ); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4220">
</A>
inv2 : IN01D1 <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
( I=>Q(2), ZN=>QN(2) ); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4222">
</A>
<A NAME="22479">
</A>
inv3 : IN01D1 <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
( I=>Q(3), ZN=>QN(3) ); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=264135">
</A>
-- Positional association for standard components:</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4232">
</A>
-- Q D Clk Rst</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4234">
</A>
<A NAME="30339">
</A>
d0: asDFF <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
(Q (0 <B CLASS="Keyword">
to</B>
0), QN(0 <B CLASS="Keyword">
to</B>
0), Trig, Reset);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4236">
</A>
d1: asDFF <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
(Q (1 <B CLASS="Keyword">
to</B>
1), QN(1 <B CLASS="Keyword">
to</B>
1), Q(0), Reset);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4238">
</A>
d2: asDFF <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
(Q (2 <B CLASS="Keyword">
to</B>
2), QN(2 <B CLASS="Keyword">
to</B>
2), Q(1), Reset);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=4240">
</A>
<A NAME="10509">
</A>
d3: asDFF <B CLASS="Keyword">
port</B>
<B CLASS="Keyword">
map</B>
(Q (3 <B CLASS="Keyword">
to</B>
3), QN(3 <B CLASS="Keyword">
to</B>
3), Q(2), Reset);</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=4250">
</A>
<B CLASS="Keyword">
end</B>
structure; </P>
<UL>
<LI CLASS="BulletList">
<A NAME="pgfId=287980">
</A>
Lines <A HREF="#22357" CLASS="XRef">
5</A>
and <A HREF="#26457" CLASS="XRef">
8</A>
. Type <SPAN CLASS="BodyComputer">
STD_LOGIC_VECTOR</SPAN>
must be used for standard component ports, because the standard components are defined using this type. </LI>
<LI CLASS="BulletList">
<A NAME="pgfId=287984">
</A>
Line <A HREF="#22357" CLASS="XRef">
5</A>
. Mode <SPAN CLASS="BodyComputer">
inout </SPAN>
has to be used for <SPAN CLASS="BodyComputer">
Q </SPAN>
since it has to be read/write and this is a structural model. You cannot use mode <SPAN CLASS="BodyComputer">
buffer</SPAN>
since the formal outputs of the standard components are declared to be of mode <SPAN CLASS="BodyComputer">
out</SPAN>
.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=4254">
</A>
Line <A HREF="#33425" CLASS="XRef">
14</A>
. This synthesis directive prevents the synthesis tool from removing the 5X drive strength inverter <SPAN CLASS="BodyComputer">
inv5x</SPAN>
. This statement ties the code to a particular synthesis tool.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=287996">
</A>
Lines <A HREF="#29936" CLASS="XRef">
16</A>
–<A HREF="#22479" CLASS="XRef">
20</A>
. Named association for the hand-instantiated library cells. The names (<SPAN CLASS="BodyComputer">
IN01D5</SPAN>
and <SPAN CLASS="BodyComputer">
IN01D1</SPAN>
) and port names (<SPAN CLASS="BodyComputer">
I</SPAN>
and <SPAN CLASS="BodyComputer">
ZN</SPAN>
) come from the cell library data book or from a template (such as the one created for the <SPAN CLASS="BodyComputer">
IN01D1</SPAN>
logic cell). These statements tie the code to a particular cell library.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=264312">
</A>
Lines <A HREF="#30339" CLASS="XRef">
23</A>
–<A HREF="#10509" CLASS="XRef">
26</A>
. Positional port mapping of the standard components. The port locations are from the synthesis standard component library documentation. These <SPAN CLASS="BodyComputer">
asDFF</SPAN>
standard components will be mapped to D flip-flop library cells. These statements tie the code to a particular synthesis tool.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=287742">
</A>
You would receive the following warning from the logic synthesizer when it synthesizes this input code (entity <SPAN CLASS="BodyComputer">
Ripple_4</SPAN>
): </P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=287745">
</A>
<SPAN CLASS="Bold">
Warning</SPAN>
: Net has more than one driver: d3_Q[0]; connected to: ripple_4_p.q[3], inv3.I, d3.Q</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=287743">
</A>
There is potentially more than one <A NAME="marker=395356">
</A>
driver on a net because <SPAN CLASS="BodyComputer">
Q</SPAN>
was declared as <SPAN CLASS="BodyComputer">
inout</SPAN>
. There are a total of four warnings of this type for each of the flip-flop outputs. You can check the output netlist to make sure that you have the logic you expected as follows (the Verilog netlist is shorter and easier to read):</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=287758">
</A>
`timescale 1ns / 10ps</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287760">
</A>
<B CLASS="Keyword">
module</B>
ripple_4_u (trig, reset, qn0_5x, q);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287762">
</A>
<B CLASS="Keyword">
input</B>
trig; <B CLASS="Keyword">
input</B>
reset; <B CLASS="Keyword">
output</B>
qn0_5x; <B CLASS="Keyword">
inout</B>
[3:0] q;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287767">
</A>
<B CLASS="Keyword">
wire</B>
[3:0] qn; <B CLASS="Keyword">
supply1</B>
VDD; <B CLASS="Keyword">
supply0</B>
VSS;</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287773">
</A>
in01d5 inv5x (.I(q[0]),.ZN(qn0_5x));</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287774">
</A>
in01d1 inv0 (.I(q[0]),.ZN(qn[0]));</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287775">
</A>
in01d1 inv1 (.I(q[1]),.ZN(qn[1]));</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287776">
</A>
in01d1 inv2 (.I(q[2]),.ZN(qn[2]));</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287777">
</A>
in01d1 inv3 (.I(q[3]),.ZN(qn[3]));</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287778">
</A>
dfctnb d0(.D(qn[0]),.CP(trig),.CDN(reset),.Q(q[0]),.QN(\d0.QN ));</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287779">
</A>
dfctnb d1(.D(qn[1]),.CP(q[0]),.CDN(reset),.Q(q[1]),.QN(\d1.QN ));</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287780">
</A>
dfctnb d2(.D(qn[2]),.CP(q[1]),.CDN(reset),.Q(q[2]),.QN(\d2.QN ));</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=287781">
</A>
dfctnb d3(.D(qn[3]),.CP(q[2]),.CDN(reset),.Q(q[3]),.QN(\d3.QN ));</P>
<P CLASS="ComputerLastLabelV">
<A NAME="pgfId=287783">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=293263">
</A>
12.6.8 Shift Registers and Clocking in VHDL</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=293264">
</A>
The following code implies a <A NAME="marker=395357">
</A>
serial-in/parallel-out (SIPO) shift register:</P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=293265">
</A>
<B CLASS="Keyword">
library</B>
IEEE;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=293266">
</A>
<B CLASS="Keyword">
use</B>
IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
; <B CLASS="Keyword">
use</B>
IEEE.NUMERIC_STD.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=293267">
</A>
<B CLASS="Keyword">
entity</B>
SIPO_1 <B CLASS="Keyword">
is port</B>
(</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=293268">
</A>
Clk : <B CLASS="Keyword">
in</B>
STD_LOGIC;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=293269">
</A>
SI : <B CLASS="Keyword">
in</B>
STD_LOGIC; -- serial in</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=293270">
</A>
PO : <B CLASS="Keyword">
buffer</B>
STD_LOGIC_VECTOR(3 <B CLASS="Keyword">
downto</B>
0)); -- parallel out</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=293271">
</A>
<B CLASS="Keyword">
end</B>
SIPO_1;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=293272">
</A>
<B CLASS="Keyword">
architecture</B>
Synthesis_1 <B CLASS="Keyword">
of</B>
SIPO_1 <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=293273">
</A>
<B CLASS="Keyword">
begin process</B>
(Clk) <B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=293274">
</A>
<B CLASS="Keyword">
if</B>
(Clk <SPAN CLASS="BodyComputer">
= '1'</SPAN>
) <B CLASS="Keyword">
then</B>
PO <= SI & PO(3 <B CLASS="Keyword">
downto</B>
1); <B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=293275">
</A>
<B CLASS="Keyword">
end</B>
<B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=293276">
</A>
<B CLASS="Keyword">
end</B>
Synthesis_1;</P>
<P CLASS="Body">
<A NAME="pgfId=293277">
</A>
Here is the Verilog structural netlist that results (<SPAN CLASS="BodyComputer">
dfntnb</SPAN>
is a positive-edge–triggered D flip-flop without clear or reset):</P>
<P CLASS="ComputerFirstLabelV">
<A NAME="pgfId=293278">
</A>
<B CLASS="Keyword">
module</B>
sipo_1_u (clk, si, po);</P>
<P CLASS="ComputerLabelV">
<A NAME="pgfId=293279">
</A>
<B CLASS="Keyword">
input</B>
clk; <B CLASS="Keyword">
input</B>
si; <B CLASS="Keyword">
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