ch12.6.htm

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INTEGER</SPAN>
 to the input of a chip! The VHDL <SPAN CLASS="BodyComputer">
case</SPAN>
, <SPAN CLASS="BodyComputer">
if</SPAN>
<A NAME="marker=395345">
 </A>
, and <SPAN CLASS="BodyComputer">
select</SPAN>
<A NAME="marker=395346">
 </A>
 statements produce similar results. Assigning <A NAME="marker=395347">
 </A>
don&#8217;t care bits (<SPAN CLASS="BodyComputer">
'x'</SPAN>
) in these statements will make it easier for the synthesizer to optimize the logic.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=3858">
 </A>
12.6.4&nbsp;Decoders in VHDL</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=392979">
 </A>
The following code implies a <A NAME="marker=395348">
 </A>
decoder:</P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=392981">
 </A>
<B CLASS="Keyword">
library </B>
<A NAME="35666">
 </A>
IEEE;<B CLASS="Keyword">
 </B>
</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=392983">
 </A>
<B CLASS="Keyword">
use</B>
<A NAME="24376">
 </A>
 IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
; <B CLASS="Keyword">
use</B>
 IEEE.NUMERIC_STD.<B CLASS="Keyword">
all</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=222863">
 </A>
<B CLASS="Keyword">
entity</B>
<A NAME="11727">
 </A>
 Decoder <B CLASS="Keyword">
is port</B>
 (enable : <B CLASS="Keyword">
in</B>
 BIT;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=3870">
 </A>
	Din: STD_LOGIC_VECTOR (2 <B CLASS="Keyword">
downto</B>
 0); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=285480">
 </A>
	Dout: <B CLASS="Keyword">
out</B>
 STD_LOGIC_VECTOR (7 <B CLASS="Keyword">
downto</B>
 0));</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=3874">
 </A>
<B CLASS="Keyword">
end</B>
 Decoder;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=3878">
 </A>
<B CLASS="Keyword">
architecture</B>
 Synthesis_1 <B CLASS="Keyword">
of</B>
 Decoder <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=3880">
 </A>
	<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=285559">
 </A>
	<B CLASS="Keyword">
with</B>
 enable <B CLASS="Keyword">
select</B>
 Dout &lt;= </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=285557">
 </A>
<A NAME="13370">
 </A>
	STD_LOGIC_VECTOR</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=285551">
 </A>
<A NAME="38163">
 </A>
	(UNSIGNED'</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=285555">
 </A>
<A NAME="14023">
 </A>
		(shift_left </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=285552">
 </A>
<A NAME="30559">
 </A>
			(&quot;00000001&quot;, TO_INTEGER (UNSIGNED(Din)) </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=285556">
 </A>
			) </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=285554">
 </A>
		)</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=285553">
 </A>
	)</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=285499">
 </A>
<B CLASS="Keyword">
	when</B>
 '1', </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=3886">
 </A>
<A NAME="23017">
 </A>
	&quot;11111111&quot; <B CLASS="Keyword">
when</B>
 '0', &quot;00000000&quot; <B CLASS="Keyword">
when</B>
 <B CLASS="Keyword">
others</B>
;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=285445">
 </A>
<B CLASS="Keyword">
end</B>
 Synthesis_1;</P>
<P CLASS="Body">
<A NAME="pgfId=222902">
 </A>
There are reasons for this seemingly complex code:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=285573">
 </A>
Line <A HREF="#35666" CLASS="XRef">
1</A>
 declares the <A NAME="marker=395349">
 </A>
IEEE library. The synthesizer does not parse the VHDL code inside the library packages, but the synthesis company should be able to guarantee that the logic will behave exactly the same way as a simulation that uses the IEEE libraries and does parse the code.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=285574">
 </A>
Line <A HREF="#24376" CLASS="XRef">
2</A>
 declares the <SPAN CLASS="BodyComputer">
STD_LOGIC_1164</SPAN>
<A NAME="marker=395350">
 </A>
 package, for <SPAN CLASS="BodyComputer">
STD_LOGIC</SPAN>
 types, and the <SPAN CLASS="BodyComputer">
NUMERIC_STD</SPAN>
 package for conversion and shift functions. The shift <SPAN CLASS="Emphasis">
operators</SPAN>
 (<SPAN CLASS="BodyComputer">
sll</SPAN>
 and so on&#8211;the infix operators) were introduced in VHDL-93, they are not defined for <SPAN CLASS="BodyComputer">
STD_LOGIC</SPAN>
 types in the 1164 standard. The shift <SPAN CLASS="Emphasis">
functions</SPAN>
 defined in <SPAN CLASS="BodyComputer">
NUMERIC_STD</SPAN>
 are not operators and are called <SPAN CLASS="BodyComputer">
shift_left</SPAN>
 and so on. Some synthesis tools support <SPAN CLASS="BodyComputer">
NUMERIC_STD</SPAN>
, but not VHDL-93.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=285598">
 </A>
Line <A HREF="#13370" CLASS="XRef">
10</A>
 performs a type conversion to <SPAN CLASS="BodyComputer">
STD_LOGIC_VECTOR</SPAN>
 from <SPAN CLASS="BodyComputer">
UNSIGNED</SPAN>
.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=285636">
 </A>
Line <A HREF="#38163" CLASS="XRef">
11</A>
 is a type qualification to tell the software that the argument to the type conversion function is type <SPAN CLASS="BodyComputer">
UNSIGNED</SPAN>
.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=285631">
 </A>
Line <A HREF="#14023" CLASS="XRef">
12</A>
 is the shift function, <SPAN CLASS="BodyComputer">
shift_left</SPAN>
, from the <SPAN CLASS="BodyComputer">
NUMERIC_STD</SPAN>
<A NAME="marker=395351">
 </A>
 package.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=285671">
 </A>
Line <A HREF="#30559" CLASS="XRef">
13</A>
 converts the <SPAN CLASS="BodyComputer">
STD_LOGIC_VECTOR</SPAN>
, <SPAN CLASS="BodyComputer">
Din</SPAN>
, to <SPAN CLASS="BodyComputer">
UNSIGNED</SPAN>
 before converting to <SPAN CLASS="BodyComputer">
INTEGER</SPAN>
. We cannot convert directly from <SPAN CLASS="BodyComputer">
STD_LOGIC_VECTOR</SPAN>
 to <SPAN CLASS="BodyComputer">
INTEGER</SPAN>
.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=285811">
 </A>
The others clause in line <A HREF="#23017" CLASS="XRef">
18</A>
 is required by the logic synthesizer even though type <SPAN CLASS="BodyComputer">
BIT</SPAN>
 may only be <SPAN CLASS="BodyComputer">
'0'</SPAN>
 or <SPAN CLASS="BodyComputer">
'1'</SPAN>
.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=285812">
 </A>
If we model a decoder using a process, we can use a <SPAN CLASS="BodyComputer">
case</SPAN>
 statement inside the process. A MUX model may be used as a decoder if the input bits are set at <SPAN CLASS="BodyComputer">
'1'</SPAN>
 (active-high decoder) or at <SPAN CLASS="BodyComputer">
'0'</SPAN>
 (active-low decoder), as in the following example:</P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=19884">
 </A>
<B CLASS="Keyword">
library</B>
 IEEE; </P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=19885">
 </A>
<B CLASS="Keyword">
use</B>
 IEEE.NUMERIC_STD.<B CLASS="Keyword">
all</B>
; <B CLASS="Keyword">
use</B>
 IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=19864">
 </A>
<B CLASS="Keyword">
entity</B>
 Concurrent_Decoder <B CLASS="Keyword">
is port</B>
 (</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=268030">
 </A>
	enable : <B CLASS="Keyword">
in</B>
 BIT;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=19866">
 </A>
	Din : <B CLASS="Keyword">
in</B>
 STD_LOGIC_VECTOR (2 <B CLASS="Keyword">
downto</B>
 0); </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=19867">
 </A>
	Dout : <B CLASS="Keyword">
out</B>
 STD_LOGIC_VECTOR (7 <B CLASS="Keyword">
downto</B>
 0));</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=19868">
 </A>
<B CLASS="Keyword">
end</B>
 Concurrent_Decoder;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=19869">
 </A>
<B CLASS="Keyword">
architecture</B>
 Synthesis_1 <B CLASS="Keyword">
of</B>
 Concurrent_Decoder <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=19870">
 </A>
<B CLASS="Keyword">
begin process</B>
 (Din, enable) </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=286405">
 </A>
<B CLASS="Keyword">
	variable</B>
 T : STD_LOGIC_VECTOR(7 <B CLASS="Keyword">
downto</B>
 0);</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=19873">
 </A>
	<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=19874">
 </A>
	<B CLASS="Keyword">
if</B>
 (enable = '1') <B CLASS="Keyword">
then </B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=173606">
 </A>
		T := &quot;00000000&quot;; T( TO_INTEGER (UNSIGNED(Din))) := '1'; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=286249">
 </A>
		Dout &lt;= T ;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=286406">
 </A>
	<B CLASS="Keyword">
else</B>
 Dout &lt;= (<B CLASS="Keyword">
others</B>
 =&gt; 'Z');</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=19878">
 </A>
	<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=19879">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=19880">
 </A>
<B CLASS="Keyword">
end</B>
 Synthesis_1;</P>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=286432">
 </A>
Notice that <SPAN CLASS="BodyComputer">
T</SPAN>
 must be a variable for proper timing of the update to the output. The <SPAN CLASS="BodyComputer">
else</SPAN>
 clause in the <SPAN CLASS="BodyComputer">
if</SPAN>
 statement is necessary to avoid inferring latches.</P>
</DIV>
<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=3908">
 </A>
12.6.5&nbsp;Adders in VHDL</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=3912">
 </A>
To add two <SPAN CLASS="EquationVariables">
n</SPAN>
-bit numbers and keep the overflow bit, we need to assign to a signal with more bits, as follows:</P>
<P CLASS="ComputerFirstLabel">
<A NAME="pgfId=286593">
 </A>
<B CLASS="Keyword">
library</B>
 IEEE; </P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=286594">
 </A>
<B CLASS="Keyword">
use</B>
 IEEE.NUMERIC_STD.<B CLASS="Keyword">
all</B>
; <B CLASS="Keyword">
use</B>
 IEEE.STD_LOGIC_1164.<B CLASS="Keyword">
all</B>
; </P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=206477">
 </A>
<B CLASS="Keyword">
entity</B>
 Adder_1 <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=206478">
 </A>
<B CLASS="Keyword">
port</B>
 (A, B: <B CLASS="Keyword">
in</B>
 UNSIGNED(3 <B CLASS="Keyword">
downto</B>
 0); C: <B CLASS="Keyword">
out</B>
 UNSIGNED(4 <B CLASS="Keyword">
downto</B>
 0));</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=3944">
 </A>
<B CLASS="Keyword">
end</B>
 Adder_1;</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=3946">
 </A>
<B CLASS="Keyword">
architecture</B>
 Synthesis_1 <B CLASS="Keyword">
of</B>
 Adder_1 <B CLASS="Keyword">
is</B>
</P>
<P CLASS="ComputerLabel">
<A NAME="pgfId=286660">
 </A>
	<B CLASS="Keyword">
begin </B>
C &lt;= ('0' &amp; A) + ('0' &amp; B);</P>
<P CLASS="ComputerLastLabel">
<A NAME="pgfId=3954">
 </A>
<B CLASS="Keyword">
end</B>
 Synthesis_1;</P>
<P CLASS="Body">
<A NAME="pgfId=3960">
 </A>
Notice that both <SPAN CLASS="BodyComputer">
A</SPAN>
 and <SPAN CLASS="BodyComputer">
B</SPAN>
 have to be <SPAN CLASS="BodyComputer">
SIGNED</SPAN>
<A NAME="marker=395352">
 </A>
 or <SPAN CLASS="BodyComputer">
UNSIGNED</SPAN>
<A NAME="marker=395353">
 </A>
 as we cannot add <SPAN CLASS="BodyComputer">
STD_LOGIC_VECTOR</SPAN>
 types directly using the IEEE packages. You will get an error if a result is a different length from the target of an assignment, as in the following example (in which the arguments are not resized):</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=294547">
 </A>
adder_1:         begin C &lt;= A + B; </P>
<P CLASS="ComputerLast">
<A NAME="pgfId=294548">
 </A>
<SPAN CLASS="Bold">
Error</SPAN>
: Width mis-match: right expression is 4 bits wide, c is 5 bits wide</P>
<P CLASS="Body">
<A NAME="pgfId=286612">
 </A>
The following code may generate three adders stacked three deep:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=3962">
 </A>
z &lt;= a + b + c + d;</P>
<P CLASS="Body">
<A NAME="pgfId=307138">