ch12.6.htm

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<TITLE> 12.6&nbsp;VHDL and Logic Synthesis</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->



<DIV>

<P>[&nbsp;<A HREF="CH12.htm">Chapter&nbsp;start</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH12.5.htm">Previous&nbsp;page</A>&nbsp;]&nbsp;[&nbsp;<A HREF="CH12.7.htm">Next&nbsp;page</A>&nbsp;]</P><!--#include file="AmazonAsic.html"--><HR></DIV>

<H1 CLASS="Heading1">

<A NAME="pgfId=3515">

 </A>

12.6&nbsp;<A NAME="14151">

 </A>

VHDL and Logic Synthesis</H1>

<P CLASS="BodyAfterHead">

<A NAME="pgfId=313781">

 </A>

Most logic synthesizers insist we follow a set of rules when we use a logic system to ensure that what we synthesize matches the behavioral description. Here is a typical set of rules for use with the IEEE VHDL nine-value system:</P>

<UL>

<LI CLASS="BulletList">

<A NAME="pgfId=313782">

 </A>

You can use logic values corresponding to states <SPAN CLASS="BodyComputer">

'1'</SPAN>

, <SPAN CLASS="BodyComputer">

'H'</SPAN>

, <SPAN CLASS="BodyComputer">

'0'</SPAN>

, and <SPAN CLASS="BodyComputer">

'L'</SPAN>

 in any manner.</LI>

<LI CLASS="BulletList">

<A NAME="pgfId=263402">

 </A>

Some synthesis tools do not accept the uninitialized logic state <SPAN CLASS="BodyComputer">

'U'</SPAN>

. </LI>

<LI CLASS="BulletList">

<A NAME="pgfId=263403">

 </A>

You can use logic states <SPAN CLASS="BodyComputer">

'Z'</SPAN>

, <SPAN CLASS="BodyComputer">

'X'</SPAN>

, <SPAN CLASS="BodyComputer">

'W'</SPAN>

, and <SPAN CLASS="BodyComputer">

'-'</SPAN>

 in signal and variable assignments in any manner. <SPAN CLASS="BodyComputer">

'Z'</SPAN>

 is synthesized to three-state logic. </LI>

<LI CLASS="BulletList">

<A NAME="pgfId=263404">

 </A>

The states <SPAN CLASS="BodyComputer">

'X'</SPAN>

, <SPAN CLASS="BodyComputer">

'W'</SPAN>

, and <SPAN CLASS="BodyComputer">

'-'</SPAN>

 are treated as unknown or don&#8217;t care values.</LI>

</UL>

<P CLASS="Body">

<A NAME="pgfId=263405">

 </A>

The values <SPAN CLASS="BodyComputer">

'Z'</SPAN>

, <SPAN CLASS="BodyComputer">

'X'</SPAN>

, <SPAN CLASS="BodyComputer">

'W'</SPAN>

, and <SPAN CLASS="BodyComputer">

'-'</SPAN>

 may be used in conditional clauses such as the comparison in an <SPAN CLASS="BodyComputer">

if</SPAN>

 or <SPAN CLASS="BodyComputer">

case</SPAN>

 statement. However, some synthesis tools will ignore them and only match surrounding <SPAN CLASS="BodyComputer">

'1'</SPAN>

 and <SPAN CLASS="BodyComputer">

'0'</SPAN>

 bits. Consequently, a synthesized design may behave differently from the simulation if a stimulus uses <SPAN CLASS="BodyComputer">

'Z'</SPAN>

, <SPAN CLASS="BodyComputer">

'X'</SPAN>

, <SPAN CLASS="BodyComputer">

'W'</SPAN>

 or <SPAN CLASS="BodyComputer">

'-'</SPAN>

. The IEEE synthesis packages provide the <SPAN CLASS="BodyComputer">

STD_MATCH</SPAN>

<A NAME="marker=395341">

 </A>

 function for comparisons.</P>

<DIV>

<H2 CLASS="Heading2">

<A NAME="pgfId=3674">

 </A>

12.6.1&nbsp;<A NAME="28801">

 </A>

Initialization and Reset</H2>

<P CLASS="BodyAfterHead">

<A NAME="pgfId=3676">

 </A>

You can use a VHDL <SPAN CLASS="BodyComputer">

process</SPAN>

<A NAME="marker=395343">

 </A>

 with a <A NAME="marker=395342">

 </A>

sensitivity list to synthesize clocked logic with a reset, as in the following code:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=3678">

 </A>

<B CLASS="Keyword">

process</B>

 (signal_1, signal_2) <B CLASS="Keyword">

begin</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=3682">

 </A>

	<B CLASS="Keyword">

if</B>

 (signal_2'EVENT <B CLASS="Keyword">

and</B>

 signal_2 = '0')</P>

<P CLASS="Computer">

<A NAME="pgfId=3684">

 </A>

		<B CLASS="Keyword">

then</B>

 -- Insert initialization and reset statements.</P>

<P CLASS="Computer">

<A NAME="pgfId=3686">

 </A>

		<B CLASS="Keyword">

elsif</B>

 (signal_1'EVENT <B CLASS="Keyword">

and</B>

 signal_1 = '1')</P>

<P CLASS="Computer">

<A NAME="pgfId=3688">

 </A>

		<B CLASS="Keyword">

then</B>

 -- Insert clocking statements.</P>

<P CLASS="Computer">

<A NAME="pgfId=3690">

 </A>

	<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

if</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=3692">

 </A>

<B CLASS="Keyword">

end process</B>

;</P>

<P CLASS="BodyAfterHead">

<A NAME="pgfId=3696">

 </A>

Using a specific pattern the synthesizer can infer that you are implying a positive-edge clock (<SPAN CLASS="BodyComputer">

signal_1</SPAN>

) and a negative-edge reset (<SPAN CLASS="BodyComputer">

signal_2</SPAN>

). In order to be able to recognize sequential logic in this way, most synthesizers restrict you to using a maximum of two edges in a sensitivity list.</P>

</DIV>

<DIV>

<H2 CLASS="Heading2">

<A NAME="pgfId=3718">

 </A>

12.6.2&nbsp;Combinational Logic Synthesis in VHDL</H2>

<P CLASS="BodyAfterHead">

<A NAME="pgfId=292722">

 </A>

In VHDL a <SPAN CLASS="Definition">

level-sensitive process</SPAN>

<A NAME="marker=292724">

 </A>

 is a <SPAN CLASS="BodyComputer">

process</SPAN>

 statement that has a sensitivity list with signals that are not tested for event attributes (<SPAN CLASS="BodyComputer">

'EVENT</SPAN>

 or <SPAN CLASS="BodyComputer">

'STABLE</SPAN>

, for example) within the <SPAN CLASS="BodyComputer">

process</SPAN>

. To synthesize combinational logic we use a VHDL level-sensitive <SPAN CLASS="BodyComputer">

process</SPAN>

 or a concurrent assignment statement. Some synthesizers do not allow reference to a signal inside a level-sensitive <SPAN CLASS="BodyComputer">

process</SPAN>

 unless that signal is in the sensitivity list. In this example, signal <SPAN CLASS="BodyComputer">

b</SPAN>

 is missing from the sensitivity list:</P>

<P CLASS="ComputerOneLine">

<A NAME="pgfId=3730">

 </A>

<B CLASS="Keyword">

entity</B>

 And_Bad <B CLASS="Keyword">

is port</B>

 (a, b: <B CLASS="Keyword">

in</B>

 BIT; c: <B CLASS="Keyword">

out</B>

 BIT); <B CLASS="Keyword">

end</B>

 And_Bad;</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=3736">

 </A>

<B CLASS="Keyword">

architecture</B>

 Synthesis_Bad <B CLASS="Keyword">

of</B>

 And_Bad <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=3738">

 </A>

<B CLASS="Keyword">

	begin process</B>

 (a) -- this should be process (a, b)</P>

<P CLASS="Computer">

<A NAME="pgfId=173995">

 </A>

<B CLASS="Keyword">

		begin </B>

c &lt;= a <B CLASS="Keyword">

and</B>

 b; </P>

<P CLASS="Computer">

<A NAME="pgfId=173996">

 </A>

<B CLASS="Keyword">

	end</B>

 <B CLASS="Keyword">

process</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=3754">

 </A>

<B CLASS="Keyword">

end</B>

 Synthesis_Bad;</P>

<P CLASS="BodyAfterHead">

<A NAME="pgfId=300026">

 </A>

This situation is similar but not exactly the same as omitting a variable from an event control in a Verilog <SPAN CLASS="BodyComputer">

always</SPAN>

 statement. Some logic synthesizers accept the VHDL version of <SPAN CLASS="BodyComputer">

And_Bad</SPAN>

 but not the Verilog version or vice versa. To ensure that the VHDL simulation will match the behavior of the synthesized logic, the logic synthesizer usually checks the sensitivity list of a level-sensitive <SPAN CLASS="BodyComputer">

process</SPAN>

 and issues a warning if signals seem to be missing.</P>

</DIV>

<DIV>

<H2 CLASS="Heading2">

<A NAME="pgfId=173316">

 </A>

12.6.3&nbsp;Multiplexers in VHDL</H2>

<P CLASS="BodyAfterHead">

<A NAME="pgfId=3764">

 </A>

Multiplexers can be synthesized using a <SPAN CLASS="BodyComputer">

case</SPAN>

<A NAME="marker=395344">

 </A>

 statement (avoiding the VHDL reserved word <SPAN CLASS="BodyComputer">

'select'</SPAN>

), as the following example illustrates:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=3766">

 </A>

<B CLASS="Keyword">

entity</B>

 Mux4 <B CLASS="Keyword">

is port</B>

 </P>

<P CLASS="Computer">

<A NAME="pgfId=223118">

 </A>

(i: BIT_VECTOR(3 <B CLASS="Keyword">

downto</B>

 0); sel: BIT_VECTOR(1 <B CLASS="Keyword">

downto</B>

 0); s: <B CLASS="Keyword">

out</B>

 BIT);</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=3774">

 </A>

<B CLASS="Keyword">

end</B>

 Mux4;</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=3778">

 </A>

<B CLASS="Keyword">

architecture</B>

 Synthesis_1 <B CLASS="Keyword">

of</B>

 Mux4 <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=3780">

 </A>

	<B CLASS="Keyword">

begin</B>

 <B CLASS="Keyword">

process</B>

(sel, i) <B CLASS="Keyword">

begin</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=3784">

 </A>

		<B CLASS="Keyword">

case</B>

 sel <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=3786">

 </A>

		<B CLASS="Keyword">

when</B>

 &quot;00&quot; =&gt; s &lt;= i(0); <B CLASS="Keyword">

when</B>

 &quot;01&quot; =&gt; s &lt;= i(1);</P>

<P CLASS="Computer">

<A NAME="pgfId=3790">

 </A>

		<B CLASS="Keyword">

when</B>

 &quot;10&quot; =&gt; s &lt;= i(2); <B CLASS="Keyword">

when</B>

 &quot;11&quot; =&gt; s &lt;= i(3);</P>

<P CLASS="Computer">

<A NAME="pgfId=3794">

 </A>

		<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

case</B>

;</P>

<P CLASS="Computer">

<A NAME="pgfId=3796">

 </A>

	<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

process</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=3798">

 </A>

<B CLASS="Keyword">

end</B>

 Synthesis_1;</P>

<P CLASS="Body">

<A NAME="pgfId=172713">

 </A>

The following code, using a concurrent signal assignment is equivalent:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=3808">

 </A>

<B CLASS="Keyword">

architecture</B>

 Synthesis_2 <B CLASS="Keyword">

of</B>

 Mux4 <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=3810">

 </A>

	<B CLASS="Keyword">

begin with</B>

 sel <B CLASS="Keyword">

select</B>

 s &lt;=</P>

<P CLASS="Computer">

<A NAME="pgfId=3814">

 </A>

		i(0) <B CLASS="Keyword">

when</B>

 &quot;00&quot;, i(1) <B CLASS="Keyword">

when</B>

 &quot;01&quot;, i(2) <B CLASS="Keyword">

when</B>

 &quot;10&quot;, i(3) <B CLASS="Keyword">

when</B>

 &quot;11&quot;;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=19646">

 </A>

<B CLASS="Keyword">

end</B>

 Synthesis_2;</P>

<P CLASS="Body">

<A NAME="pgfId=19647">

 </A>

In VHDL the <SPAN CLASS="BodyComputer">

case</SPAN>

 statement must be exhaustive in either form, so there is no question of any priority in the choices as there may be in Verilog. </P>

<P CLASS="Body">

<A NAME="pgfId=285383">

 </A>

For larger MUXes we can use an array, as in the following example:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=19713">

 </A>

<B CLASS="Keyword">

library</B>

 IEEE; <B CLASS="Keyword">

use</B>

  ieee.std_logic_1164.<B CLASS="Keyword">

all</B>

;</P>

<P CLASS="Computer">

<A NAME="pgfId=3828">

 </A>

<B CLASS="Keyword">

entity</B>

 Mux8 <B CLASS="Keyword">

is port</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=172675">

 </A>

	(InBus : <B CLASS="Keyword">

in</B>

 STD_LOGIC_VECTOR(7 <B CLASS="Keyword">

downto</B>

 0);</P>

<P CLASS="Computer">

<A NAME="pgfId=3832">

 </A>

	Sel : <B CLASS="Keyword">

in</B>

 INTEGER<B CLASS="Keyword">

 range</B>

 0 to 7;</P>

<P CLASS="Computer">

<A NAME="pgfId=9188">

 </A>

	OutBit : <B CLASS="Keyword">

out</B>

 STD_LOGIC);</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=3836">

 </A>

<B CLASS="Keyword">

end</B>

 Mux8;</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=3840">

 </A>

<B CLASS="Keyword">

architecture</B>

 Synthesis_1 <B CLASS="Keyword">

of</B>

 Mux8 <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=3842">

 </A>

	<B CLASS="Keyword">

begin</B>

 <B CLASS="Keyword">

process</B>

(InBus, Sel)</P>

<P CLASS="Computer">

<A NAME="pgfId=3846">

 </A>

	<B CLASS="Keyword">

begin </B>

OutBit &lt;= InBus(Sel); </P>

<P CLASS="Computer">

<A NAME="pgfId=3852">

 </A>

	<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

process</B>

; </P>

<P CLASS="Computer">

<A NAME="pgfId=3854">

 </A>

<B CLASS="Keyword">

end</B>

 Synthesis_1;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=409942">

 </A>

&nbsp;</P>

<P CLASS="BodyAfterHead">

<A NAME="pgfId=172694">

 </A>

Most synthesis tools can infer that, in this case, <SPAN CLASS="BodyComputer">

Sel</SPAN>

 requires three bits. If not, you have to declare the signal as a <SPAN CLASS="BodyComputer">

STD_LOGIC_VECTOR</SPAN>

,</P>

<P CLASS="ComputerOneLine">

<A NAME="pgfId=222801">

 </A>

	Sel : <B CLASS="Keyword">

in</B>

 STD_LOGIC_VECTOR(2 <B CLASS="Keyword">

downto </B>

0);</P>

<P CLASS="BodyAfterHead">

<A NAME="pgfId=222799">

 </A>

and use a conversion routine from the <SPAN CLASS="BodyComputer">

STD_NUMERIC</SPAN>

 package like this:</P>

<P CLASS="ComputerOneLine">

<A NAME="pgfId=261035">

 </A>

OutBit &lt;= InBus(TO_INTEGER ( UNSIGNED (Sel) ) ) ;</P>

<P CLASS="BodyAfterHead">

<A NAME="pgfId=261037">

 </A>

At some point you have to convert from an <SPAN CLASS="BodyComputer">

INTEGER</SPAN>

 to <SPAN CLASS="BodyComputer">

BIT</SPAN>

 logic anyway, since you cannot connect an <SPAN CLASS="BodyComputer">
12345

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