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<TITLE> 12.1 A Logic-Synthesis Example</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
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<H1 CLASS="Heading1">
<A NAME="pgfId=262614">
</A>
12.1 <A NAME="14786">
</A>
A Logic-Synthesis Example</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=262615">
</A>
As an example of logic synthesis, we will compare two implementations of the <A NAME="marker=395376">
</A>
Viterbi decoder described in Chapter 11. Both versions used logic cells from a VLSI Technology cell library. The first ASIC was designed by hand using schematic entry and a data book. The second version of the ASIC (the one that was fabricated) used Verilog for design entry and a logic synthesizer. <A HREF="#37264" CLASS="XRef">
Table 12.1</A>
compares the two versions. The synthesized ASIC is 16 percent smaller and 13 percent faster than the hand-designed version.</P>
<P CLASS="Body">
<A NAME="pgfId=262079">
</A>
How does logic synthesis generate smaller and faster circuits? <A HREF="#40122" CLASS="XRef">
Figure 12.1</A>
shows the schematic for a hand-designed comparator and MUX used in the Viterbi decoder ASIC, called here the <A NAME="marker=395377">
</A>
comparator/MUX example. The Verilog code and the schematic in <A HREF="#40122" CLASS="XRef">
Figure 12.1</A>
describe the same function. The comparison, in <A HREF="#31858" CLASS="XRef">
Table 12.2</A>
, of the two design approaches shows that the synthesized version is smaller and faster than the hand design, even though the synthesized design uses more cells.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=396201">
</A>
TABLE 12.1 <A NAME="37264">
</A>
A comparison of hand design with synthesis (using a 1.0 <SPAN CLASS="Symbol">
m</SPAN>
m VLSI Technology cell library).</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=396212">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=396214">
</A>
<SPAN CLASS="TableHeads">
Path delay/ <BR>
ns</SPAN>
<SUP CLASS="Superscript">
(</SUP>
<SPAN CLASS="TableHeads">
<A HREF="#pgfId=396217" CLASS="footnote">
1</A>
</SPAN>
<SUP CLASS="Superscript">
)</SUP>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=396219">
</A>
<SPAN CLASS="TableHeads">
No. of standard cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=396221">
</A>
<SPAN CLASS="TableHeads">
No. of transistors</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=396223">
</A>
<SPAN CLASS="TableHeads">
Chip area/ <BR>
mils</SPAN>
<SUP CLASS="Superscript">
2 (</SUP>
<SPAN CLASS="TableHeads">
<A HREF="#pgfId=396226" CLASS="footnote">
2</A>
</SPAN>
<SUP CLASS="Superscript">
)</SUP>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=396228">
</A>
Hand design</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=396230">
</A>
41.6</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=396232">
</A>
1,359</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=396234">
</A>
16,545</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=396236">
</A>
21,877</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeftEnd">
<A NAME="pgfId=396238">
</A>
Synthesized design</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=396240">
</A>
36.3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=396242">
</A>
1,493</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=396244">
</A>
11,946</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=396246">
</A>
18,322</P>
</TD>
</TR>
</TABLE>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="3">
<P CLASS="Table">
<A NAME="pgfId=360441">
</A>
</P>
<DIV>
<IMG SRC="CH12-1.gif">
</DIV>
</TD>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="Computer">
<A NAME="pgfId=360447">
</A>
</P>
<P CLASS="Computer">
<A NAME="pgfId=391854">
</A>
// comp_mux.v<B CLASS="Keyword">
</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=360448">
</A>
<B CLASS="Keyword">
module</B>
comp_mux(a, b, outp);</P>
<P CLASS="Computer">
<A NAME="pgfId=360449">
</A>
<B CLASS="Keyword">
input</B>
[2:0] a, b;</P>
<P CLASS="Computer">
<A NAME="pgfId=360450">
</A>
<B CLASS="Keyword">
output</B>
[2:0] outp; </P>
<P CLASS="Computer">
<A NAME="pgfId=360451">
</A>
<B CLASS="Keyword">
function</B>
[2:0] compare; </P>
<P CLASS="Computer">
<A NAME="pgfId=360452">
</A>
<B CLASS="Keyword">
input</B>
[2:0] ina, inb;</P>
<P CLASS="Computer">
<A NAME="pgfId=360453">
</A>
<B CLASS="Keyword">
begin </B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=360454">
</A>
<B CLASS="Keyword">
if</B>
(ina <= inb) compare = ina;</P>
<P CLASS="Computer">
<A NAME="pgfId=360455">
</A>
<B CLASS="Keyword">
else</B>
compare = inb; </P>
<P CLASS="Computer">
<A NAME="pgfId=360456">
</A>
<B CLASS="Keyword">
end</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=360457">
</A>
<B CLASS="Keyword">
endfunction </B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=360458">
</A>
<B CLASS="Keyword">
assign</B>
outp = compare(a, b);</P>
<P CLASS="Computer">
<A NAME="pgfId=360459">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=360504">
</A>
FIGURE 12.1 <A NAME="40122">
</A>
Schematic and HDL design entry.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=360464">
</A>
TABLE 12.2 <A NAME="31858">
</A>
Comparison of the comparator/MUX designs using a 1.0 <SPAN CLASS="Symbol">
m</SPAN>
m standard-cell library.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=360474">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=360476">
</A>
<SPAN CLASS="TableHeads">
Delay /ns</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=360478">
</A>
<SPAN CLASS="TableHeads">
No. of standard cells</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=360480">
</A>
<SPAN CLASS="TableHeads">
No. of transistors</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=360482">
</A>
<SPAN CLASS="TableHeads">
Area /mils</SPAN>
<SUP CLASS="Superscript">
2</SUP>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=360484">
</A>
Hand design</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=360486">
</A>
4.3</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=360488">
</A>
12</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=360490">
</A>
116</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=360492">
</A>
68.68</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=360494">
</A>
Synthesized</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=360496">
</A>
2.9</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=360498">
</A>
15</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=360500">
</A>
66</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLast">
<A NAME="pgfId=360502">
</A>
46.43</P>
</TD>
</TR>
</TABLE>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=396217">
</A>
These delays are under nominal operating conditions with no wiring capacitance. This is the only stage at which a comparison could be made because the hand design was not completed.</P>
</DIV>
<DIV CLASS="footnote">
<P CLASS="TableFootLast">
<SPAN CLASS="footnoteNumber">
2.</SPAN>
<A NAME="pgfId=396226">
</A>
Both figures are initial layout estimates using default power-bus and signal routing widths.</P>
</DIV>
</DIV>
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