ch12.e.htm

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 </A>
<B CLASS="Keyword">
end</B>
 Synthesis_2;</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=277079">
 </A>
Try to synthesize both versions. Does the synthesizer accept the code? <SPAN CLASS="Emphasis">
Hint:</SPAN>
 It should not. Explain any problems that you encounter, and how to correct them. Resynthesize your working code.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=277257">
 </A>
12.26&nbsp;(*VHDL <A NAME="marker=395406">
 </A>
data slip, 60  min.) Consider the following process, a shift register core:</P>
<P CLASS="Computer">
<A NAME="pgfId=277258">
 </A>
S1: <B CLASS="Keyword">
process </B>
(data, enable) <B CLASS="Keyword">
begin</B>
 </P>
<P CLASS="Computer">
<A NAME="pgfId=277259">
 </A>
<B CLASS="Keyword">
if</B>
 enable = '1' <B CLASS="Keyword">
then </B>
Q &lt;= Q(7 <B CLASS="Keyword">
downto</B>
 0) &amp; data; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=277260">
 </A>
<B CLASS="Keyword">
end process</B>
; </P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=277261">
 </A>
Complete the VHDL code and simulate to ensure your model operates correctly. Try to synthesize your code and compare the operation of the resulting implementation with the simulation results. Explain any problems you encounter.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=277764">
 </A>
12.27&nbsp;(**Synchronous logic, hours) Investigate the following alternative ways to synthesize synchronous logic in VHDL. <SPAN CLASS="Emphasis">
Hint:</SPAN>
 A few of these methods are illegal in both VHDL-87 and VHDL-93, some methods are only illegal in VHDL-87. Create a table for <SPAN CLASS="BodyComputer">
Q1-Q17</SPAN>
 that summarizes your results. Assume all signals are <SPAN CLASS="BodyComputer">
STD_LOGIC</SPAN>
. Can you create any more methods (positive-edge only)?</P>
<P CLASS="Computer">
<A NAME="pgfId=277765">
 </A>
-- Let me count the ways to count.</P>
<P CLASS="Computer">
<A NAME="pgfId=277766">
 </A>
-- Using wait statement:</P>
<P CLASS="Computer">
<A NAME="pgfId=277767">
 </A>
<B CLASS="Keyword">
process</B>
 <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
wait</B>
 <B CLASS="Keyword">
on</B>
 clk; Q1 &lt;= D; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
; -- 2 edges</P>
<P CLASS="Computer">
<A NAME="pgfId=277768">
 </A>
<B CLASS="Keyword">
process</B>
 <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
wait</B>
 <B CLASS="Keyword">
on</B>
 clk <B CLASS="Keyword">
until</B>
 clk = '1'; Q2 &lt;= D; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277769">
 </A>
<B CLASS="Keyword">
process</B>
 <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
wait</B>
 <B CLASS="Keyword">
until</B>
 clk = '1'; Q3 &lt;= D; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277770">
 </A>
<B CLASS="Keyword">
process</B>
 <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
wait</B>
 <B CLASS="Keyword">
until</B>
 clk = '1' <B CLASS="Keyword">
and</B>
 clk'EVENT; Q4 &lt;= D;</P>
<P CLASS="Computer">
<A NAME="pgfId=291072">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277771">
 </A>
-- Using process and sensitivity list:</P>
<P CLASS="Computer">
<A NAME="pgfId=277772">
 </A>
<B CLASS="Keyword">
process</B>
(clk) <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
if</B>
 clk'EVENT <B CLASS="Keyword">
and</B>
 clk = '1' <B CLASS="Keyword">
then</B>
 Q5 &lt;= D; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=290933">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277773">
 </A>
<B CLASS="Keyword">
process</B>
(clk) <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
if</B>
 <B CLASS="Keyword">
not</B>
 clk'STABLE <B CLASS="Keyword">
and</B>
 clk = '1' <B CLASS="Keyword">
then</B>
 Q6 &lt;= D;</P>
<P CLASS="Computer">
<A NAME="pgfId=291064">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277774">
 </A>
<B CLASS="Keyword">
process</B>
(clk) <B CLASS="Keyword">
begin</B>
 </P>
<P CLASS="Computer">
<A NAME="pgfId=277775">
 </A>
<B CLASS="Keyword">
if</B>
 clk'LAST_VALUE = '0' <B CLASS="Keyword">
and</B>
 clk = '1' <B CLASS="Keyword">
then</B>
 Q7 &lt;= D; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277776">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277777">
 </A>
-- Using rising_edge function from STD_LOGIC_1164:</P>
<P CLASS="Computer">
<A NAME="pgfId=277778">
 </A>
<B CLASS="Keyword">
process</B>
(clk) <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
if</B>
 rising_edge(clk) <B CLASS="Keyword">
then</B>
 Q8 &lt;= D; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
; </P>
<P CLASS="Computer">
<A NAME="pgfId=290975">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277779">
 </A>
<B CLASS="Keyword">
process</B>
 <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
wait</B>
 <B CLASS="Keyword">
until</B>
 rising_edge(clk); Q9 &lt;= D; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277780">
 </A>
<B CLASS="Keyword">
process</B>
 <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
wait</B>
 <B CLASS="Keyword">
on</B>
 rising_edge(clk); Q10 &lt;= D; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277781">
 </A>
-- rising_edge expanded:</P>
<P CLASS="Computer">
<A NAME="pgfId=277782">
 </A>
<B CLASS="Keyword">
process</B>
(clk) <B CLASS="Keyword">
begin</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=277783">
 </A>
<B CLASS="Keyword">
if</B>
 clk'EVENT <B CLASS="Keyword">
and</B>
 To_X01(clk) = '1' </P>
<P CLASS="Computer">
<A NAME="pgfId=290955">
 </A>
<B CLASS="Keyword">
	and</B>
 To_X01(clk'LAST_VALUE) = '0' <B CLASS="Keyword">
then</B>
 Q11 &lt;= D; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
if</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277785">
 </A>
<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=277786">
 </A>
-- Using concurrent signal assignments:</P>
<P CLASS="Computer">
<A NAME="pgfId=277787">
 </A>
Q12 &lt;= D <B CLASS="Keyword">
when</B>
 clk'EVENT <B CLASS="Keyword">
and</B>
 clk = '1'; -- VHDL-93 only (...else)</P>
<P CLASS="Computer">
<A NAME="pgfId=277788">
 </A>
Q13 &lt;= D <B CLASS="Keyword">
when</B>
 clk'EVENT <B CLASS="Keyword">
and</B>
 clk = '1' <B CLASS="Keyword">
else</B>
 Q13; -- need buffer</P>
<P CLASS="Computer">
<A NAME="pgfId=277789">
 </A>
Q14 &lt;= D <B CLASS="Keyword">
when</B>
 clk'EVENT <B CLASS="Keyword">
and</B>
 clk = '1' <B CLASS="Keyword">
else</B>
 <B CLASS="Keyword">
unaffected</B>
; -- VHDL-93</P>
<P CLASS="Computer">
<A NAME="pgfId=277790">
 </A>
Q15 &lt;= D <B CLASS="Keyword">
when</B>
 clk'EVENT <B CLASS="Keyword">
and</B>
 clk = '1' </P>
<P CLASS="Computer">
<A NAME="pgfId=291168">
 </A>
<B CLASS="Keyword">
	else</B>
 Q15'DRIVING_VALUE; -- VHDL-93</P>
<P CLASS="Computer">
<A NAME="pgfId=395105">
 </A>
-- Using blocks:</P>
<P CLASS="Computer">
<A NAME="pgfId=395106">
 </A>
F1:<B CLASS="Keyword">
block</B>
(<B CLASS="Keyword">
not</B>
 clk'STABLE <B CLASS="Keyword">
and</B>
 clk = '1') </P>
<P CLASS="Computer">
<A NAME="pgfId=395110">
 </A>
<B CLASS="Keyword">
		begin</B>
 Q16 &lt;=<B CLASS="Keyword">
 guarded</B>
 D;<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
block</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=395107">
 </A>
F2:<B CLASS="Keyword">
block</B>
(clk'EVENT <B CLASS="Keyword">
and</B>
 clk = '1') </P>
<P CLASS="Computer">
<A NAME="pgfId=395111">
 </A>
<B CLASS="Keyword">
		begin</B>
 Q17 &lt;= <B CLASS="Keyword">
guarded</B>
 D;<B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
block</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=291222">
 </A>
-- The bizarre and variations using '0', 'L', 'H', and '1':</P>
<P CLASS="Computer">
<A NAME="pgfId=291225">
 </A>
<B CLASS="Keyword">
process</B>
(clk) <B CLASS="Keyword">
begin</B>
 </P>
<P CLASS="Computer">
<A NAME="pgfId=291226">
 </A>
<B CLASS="Keyword">
if</B>
 clk'LAST_VALUE = 'L' <B CLASS="Keyword">
and</B>
 clk = 'H' <B CLASS="Keyword">
or</B>
 clk = '1' <B CLASS="Keyword">
then</B>
 Q18 &lt;= D; </P>
<P CLASS="Computer">
<A NAME="pgfId=291261">
 </A>
<B CLASS="Keyword">
	end</B>
 <B CLASS="Keyword">
if</B>
; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="Computer">
<A NAME="pgfId=291237">
 </A>
<B CLASS="Keyword">
process</B>
 <B CLASS="Keyword">
begin</B>
 <B CLASS="Keyword">
wait</B>
 <B CLASS="Keyword">
until</B>
 clk = 'H' <B CLASS="Keyword">
or</B>
 clk = '1';</P>
<P CLASS="Computer">
<A NAME="pgfId=291250">
 </A>
Q19 &lt;= D; <B CLASS="Keyword">
end</B>
 <B CLASS="Keyword">
process</B>
;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=277794">
 </A>
-- More?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=277795">
 </A>
12.28&nbsp;(*State assignment, 30  min) If we have a state machine with <SPAN CLASS="EquationVariables">
r</SPAN>
 states and <SPAN CLASS="EquationVariables">
S</SPAN>
<SUB CLASS="Subscript">
0</SUB>
 variables, how many different state assignments are there, for <SPAN CLASS="EquationVariables">
S</SPAN>
<SUB CLASS="Subscript">
0</SUB>
  =  1 and <SPAN CLASS="EquationVariables">
r</SPAN>
  =  2? List the different state assignments with <SPAN CLASS="EquationVariables">
S</SPAN>
<SUB CLASS="Subscript">
0</SUB>
  =  2, <SPAN CLASS="EquationVariables">
r</SPAN>
  =  3 and for <SPAN CLASS="EquationVariables">
S</SPAN>
<SUB CLASS="Subscript">
0</SUB>
  =  2, <SPAN CLASS="EquationVariables">
r</SPAN>
  =  4. How many of these are distinct? For five states and three state variables there are 6720 different state assignments, of which 140 are distinct. For nine states and four state variables there are over 4  <SPAN CLASS="Symbol">
&#165;</SPAN>
  10<SUP CLASS="Superscript">
9</SUP>
 different possible state assignments and nearly 11  million of these are distinct. This makes the task of performing sequential logic synthesis by exhaustively considering all possible state assignments virtually impossible. <SPAN CLASS="Emphasis">
Hint:</SPAN>
 McCluskey&#8217;s book discusses the problem of state assignment [<A NAME="[McCluskey, 1965]">
 </A>
1965, pp.&nbsp;266&#8211;267].</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=332870">
 </A>
12.29&nbsp;(*Synthesis scripts, hours)&nbsp;Write and document a script to synthesize the Viterbi decoder using a logic synthesizer of your choice.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=332868">
 </A>
12.30&nbsp;(*Floorplanning, hours)&nbsp;Write and document a script to perform timing-driven synthesis and floorplanning for the Viterbi decoder.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=395059">
 </A>
12.31&nbsp;(***Patents, 120  min.)&nbsp;Obtain a copy of U.S. Patent 5,530,841 &#8220;Method for converting a hardware independent user description of a logic circuit into hardware components.&#8221; This patent caused controversy during the approval of the IEEE synthesis packages. Research this topic (including a visit to the Web site of the synthesis package working group and checking other synthesis patents). Do you feel (as an engineer) that the IEEE should be concerned?</P>
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