ch12.e.htm

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 (sel) outp &lt;= 0; <B CLASS="Keyword">

end</B>

</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=276429">

 </A>

<B CLASS="Keyword">

endmodule</B>

 </P>

<P CLASS="ExerciseNoIndent">

<A NAME="pgfId=276430">

 </A>

Write a module to drive <SPAN CLASS="BodyComputer">

TestAssign1</SPAN>

 and simulate your code. Now consider the following modification (call this <SPAN CLASS="BodyComputer">

TestAssign2</SPAN>

):</P>

<P CLASS="ComputerOneLine">

<A NAME="pgfId=276431">

 </A>

<B CLASS="Keyword">

	if</B>

 (sel) outp &lt;= 0; <B CLASS="Keyword">

else</B>

 outp &lt;= 1;</P>

<P CLASS="ExerciseNoIndent">

<A NAME="pgfId=276432">

 </A>

Simulate <SPAN CLASS="BodyComputer">

TestAssign2</SPAN>

 and compare your results. Try to synthesize <SPAN CLASS="BodyComputer">

TestAssign1</SPAN>

 and <SPAN CLASS="BodyComputer">

TestAssign2</SPAN>

. Comment on any problems you have and how you resolved them. Compare the behavior of the synthesized logic with the simulations.</P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=276747">

 </A>

12.21&nbsp;(VHDL sequential logic, 60  min.) Consider the following processes:</P>

<P CLASS="Computer">

<A NAME="pgfId=276748">

 </A>

S1: <B CLASS="Keyword">

process </B>

(clk) <B CLASS="Keyword">

begin</B>

 </P>

<P CLASS="Computer">

<A NAME="pgfId=276749">

 </A>

<B CLASS="Keyword">

if</B>

 clk'EVENT <B CLASS="Keyword">

and</B>

 clk = '1' <B CLASS="Keyword">

then </B>

count &lt;= count + inc; <B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

if</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=276750">

 </A>

<B CLASS="Keyword">

end process</B>

; </P>

<P CLASS="Computer">

<A NAME="pgfId=276751">

 </A>

S2: <B CLASS="Keyword">

process </B>

(clk) <B CLASS="Keyword">

begin</B>

 </P>

<P CLASS="Computer">

<A NAME="pgfId=276752">

 </A>

	<B CLASS="Keyword">

if</B>

 rst = '1' <B CLASS="Keyword">

then </B>

count &lt;= 0;</P>

<P CLASS="Computer">

<A NAME="pgfId=276753">

 </A>

	<B CLASS="Keyword">

elsif</B>

 clk'EVENT <B CLASS="Keyword">

and</B>

 clk = '1' <B CLASS="Keyword">

then </B>

count &lt;= count + inc;</P>

<P CLASS="Computer">

<A NAME="pgfId=276754">

 </A>

<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

if</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=276755">

 </A>

<B CLASS="Keyword">

end process</B>

; </P>

<P CLASS="Computer">

<A NAME="pgfId=276756">

 </A>

S3: <B CLASS="Keyword">

process </B>

(clk, rst) <B CLASS="Keyword">

begin</B>

 </P>

<P CLASS="Computer">

<A NAME="pgfId=276757">

 </A>

	<B CLASS="Keyword">

if</B>

 rst = '1' <B CLASS="Keyword">

then </B>

count &lt;= 0; <B CLASS="Keyword">

elsif</B>

 clk'EVENT <B CLASS="Keyword">

and</B>

 clk = '1' <B CLASS="Keyword">

then </B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=276758">

 </A>

		count &lt;= count + inc; sum &lt;= count + sum;</P>

<P CLASS="Computer">

<A NAME="pgfId=276759">

 </A>

	<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

if</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=276760">

 </A>

<B CLASS="Keyword">

end process</B>

; </P>

<P CLASS="Computer">

<A NAME="pgfId=276761">

 </A>

S4: <B CLASS="Keyword">

process </B>

(clk) <B CLASS="Keyword">

begin</B>

 </P>

<P CLASS="Computer">

<A NAME="pgfId=276762">

 </A>

<B CLASS="Keyword">

if</B>

 clk'EVENT <B CLASS="Keyword">

and</B>

 clk = '1' <B CLASS="Keyword">

then if</B>

 rst = '1' <B CLASS="Keyword">

then </B>

count &lt;= 0;</P>

<P CLASS="Computer">

<A NAME="pgfId=276763">

 </A>

<B CLASS="Keyword">

	else</B>

 count &lt;= count + inc; <B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

if</B>

;</P>

<P CLASS="Computer">

<A NAME="pgfId=276764">

 </A>

<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

if</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=276765">

 </A>

<B CLASS="Keyword">

end process</B>

; </P>

<P CLASS="Computer">

<A NAME="pgfId=276766">

 </A>

S5: <B CLASS="Keyword">

process </B>

(clk, rst) <B CLASS="Keyword">

begin</B>

 </P>

<P CLASS="Computer">

<A NAME="pgfId=276767">

 </A>

<B CLASS="Keyword">

if</B>

 rst = '1' <B CLASS="Keyword">

then </B>

count &lt;= 0;</P>

<P CLASS="Computer">

<A NAME="pgfId=276768">

 </A>

<B CLASS="Keyword">

elsif</B>

 clk'EVENT <B CLASS="Keyword">

and</B>

 clk = '1' <B CLASS="Keyword">

then </B>

count &lt;= count + inc;</P>

<P CLASS="Computer">

<A NAME="pgfId=276769">

 </A>

<B CLASS="Keyword">

else</B>

 count &lt;= count + 1;</P>

<P CLASS="Computer">

<A NAME="pgfId=276770">

 </A>

<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

if</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=276771">

 </A>

<B CLASS="Keyword">

end process</B>

; </P>

<P CLASS="Computer">

<A NAME="pgfId=276772">

 </A>

S6: <B CLASS="Keyword">

process </B>

(clk, rst) <B CLASS="Keyword">

begin</B>

 </P>

<P CLASS="Computer">

<A NAME="pgfId=276773">

 </A>

	<B CLASS="Keyword">

if</B>

 rst = '1' <B CLASS="Keyword">

then </B>

count &lt;= 0;</P>

<P CLASS="Computer">

<A NAME="pgfId=276774">

 </A>

	<B CLASS="Keyword">

elsif</B>

 clk'EVENT <B CLASS="Keyword">

and</B>

 clk = '1' <B CLASS="Keyword">

then </B>

count &lt;= count + inc;</P>

<P CLASS="Computer">

<A NAME="pgfId=276775">

 </A>

	<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

if</B>

; inc &lt;= not dec;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=276776">

 </A>

<B CLASS="Keyword">

end process</B>

; </P>

<P CLASS="Exercise">

<A NAME="pgfId=276777">

 </A>

Write code to drive each of these processes and simulate them. Explain any errors or problems you encounter. Try to synthesize your code and check that the results behave correctly and match the simulation results. Explain any differences in behavior or any problems you encounter.</P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=276845">

 </A>

12.22&nbsp;(Verilog signed <A NAME="marker=395404">

 </A>

multiplication, 30  min.) Show, by simulation, that the following code performs signed multiplication. Synthesize the code and compare the results with the simulation.</P>

<P CLASS="Computer">

<A NAME="pgfId=276846">

 </A>

<B CLASS="Keyword">

module </B>

Smpy (in1, in2, out); <B CLASS="Keyword">

input</B>

 [2:0] in1, in2; <B CLASS="Keyword">

output</B>

 [5:0] out;</P>

<P CLASS="Computer">

<A NAME="pgfId=276847">

 </A>

<B CLASS="Keyword">

assign</B>

 out = {{3{in1[2]}},in1}*{{3{in2[2]}},in2};</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=276848">

 </A>

<B CLASS="Keyword">

endmodule</B>

 </P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=277002">

 </A>

12.23&nbsp;<A NAME="32303">

 </A>

(Verilog arithmetic, 30  min.) Synthesize the following code and explain in detail the implementation that results:</P>

<P CLASS="Computer">

<A NAME="pgfId=277003">

 </A>

<B CLASS="Keyword">

module </B>

Arithmetic (in_4, out_2, out_3, out_7, out_14);</P>

<P CLASS="Computer">

<A NAME="pgfId=277004">

 </A>

<B CLASS="Keyword">

input</B>

 [3:0] in_4; <B CLASS="Keyword">

output</B>

 [7:0] out_2, out_3, out_7, out_14;</P>

<P CLASS="Computer">

<A NAME="pgfId=277005">

 </A>

<B CLASS="Keyword">

assign</B>

 out_2 = in_4*2; <B CLASS="Keyword">

assign</B>

 out_3 = in_4*3; <B CLASS="Keyword">

assign</B>

 out_7 = in_4*7;</P>

<P CLASS="Computer">

<A NAME="pgfId=277006">

 </A>

<B CLASS="Keyword">

assign</B>

 out_14 = in_4 * 4'b1110;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=277007">

 </A>

<B CLASS="Keyword">

endmodule</B>

 </P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=277047">

 </A>

12.24&nbsp;(Verilog <A NAME="marker=395405">

 </A>

overflow bit, 15  min.) Synthesize the following code and explain the implementation that results:</P>

<P CLASS="Computer">

<A NAME="pgfId=277048">

 </A>

<B CLASS="Keyword">

module </B>

Overflow (a, b, sum, cout); </P>

<P CLASS="Computer">

<A NAME="pgfId=277049">

 </A>

<B CLASS="Keyword">

input</B>

 [7:0] a, b; <B CLASS="Keyword">

output</B>

 [7:0] sum; <B CLASS="Keyword">

output</B>

 cout;</P>

<P CLASS="Computer">

<A NAME="pgfId=277050">

 </A>

<B CLASS="Keyword">

assign</B>

 {cout, sum} = a + b;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=277051">

 </A>

<B CLASS="Keyword">

endmodule</B>

 </P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=277059">

 </A>

12.25&nbsp;(*VHDL latches, 60  min.) Consider the following two architectures:</P>

<P CLASS="Computer">

<A NAME="pgfId=277060">

 </A>

<B CLASS="Keyword">

entity</B>

 latch1 <B CLASS="Keyword">

is port</B>

(data: <B CLASS="Keyword">

in</B>

 BIT_VECTOR(1 <B CLASS="Keyword">

to</B>

 4);</P>

<P CLASS="Computer">

<A NAME="pgfId=277061">

 </A>

	reset: <B CLASS="Keyword">

in</B>

 BIT; delay: <B CLASS="Keyword">

out</B>

 BIT_VECTOR(1 <B CLASS="Keyword">

to</B>

 4));</P>

<P CLASS="Computer">

<A NAME="pgfId=277062">

 </A>

<B CLASS="Keyword">

end</B>

 latch1;</P>

<P CLASS="Computer">

<A NAME="pgfId=277063">

 </A>

<B CLASS="Keyword">

architecture</B>

 Synthesis_1 <B CLASS="Keyword">

of</B>

 latch1 <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=277064">

 </A>

<B CLASS="Keyword">

begin</B>

 S1: <B CLASS="Keyword">

process </B>

(data, reset) <B CLASS="Keyword">

variable</B>

 hold : BIT_VECTOR (1 <B CLASS="Keyword">

to</B>

 4);</P>

<P CLASS="Computer">

<A NAME="pgfId=277065">

 </A>

<B CLASS="Keyword">

begin</B>

 </P>

<P CLASS="Computer">

<A NAME="pgfId=277066">

 </A>

<B CLASS="Keyword">

	if</B>

 reset = '1' <B CLASS="Keyword">

then </B>

hold := &quot;0000&quot;; <B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

if</B>

; </P>

<P CLASS="Computer">

<A NAME="pgfId=277067">

 </A>

	delay &lt;= hold; hold := data;</P>

<P CLASS="Computer">

<A NAME="pgfId=277068">

 </A>

<B CLASS="Keyword">

end process</B>

; </P>

<P CLASS="ComputerLast">

<A NAME="pgfId=277069">

 </A>

<B CLASS="Keyword">

end</B>

 Synthesis_1;</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=277070">

 </A>

<B CLASS="Keyword">

architecture</B>

 Synthesis_2 <B CLASS="Keyword">

of</B>

 latch1 <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=277071">

 </A>

<B CLASS="Keyword">

begin</B>

 S2: <B CLASS="Keyword">

process </B>

(data, enable, reset) </P>

<P CLASS="Computer">

<A NAME="pgfId=277072">

 </A>

<B CLASS="Keyword">

variable</B>

 hold : BIT_VECTOR (1 <B CLASS="Keyword">

to</B>

 4);</P>

<P CLASS="Computer">

<A NAME="pgfId=277073">

 </A>

<B CLASS="Keyword">

begin</B>

 </P>

<P CLASS="Computer">

<A NAME="pgfId=277074">

 </A>

<B CLASS="Keyword">

if</B>

 enable = '1' <B CLASS="Keyword">

then </B>

hold := data; <B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

if</B>

;</P>

<P CLASS="Computer">

<A NAME="pgfId=277075">

 </A>

delay &lt;= hold;</P>

<P CLASS="Computer">

<A NAME="pgfId=277076">

 </A>

<B CLASS="Keyword">

if</B>

 reset = '0' <B CLASS="Keyword">

then </B>

hold := &quot;0000&quot;;</P>

<P CLASS="Computer">

<A NAME="pgfId=277077">

 </A>

<B CLASS="Keyword">

end process</B>

; </P>

<P CLASS="ComputerLast">

<A NAME="pgfId=277078">
1234

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