ch12.e.htm

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 </A>

<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

process</B>

;</P>

<P CLASS="Exercise">

<A NAME="pgfId=274839">

 </A>

What is the error message? Synthesize this code, and explain the results:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=274840">

 </A>

<B CLASS="Keyword">

process begin</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=274841">

 </A>

	<B CLASS="Keyword">

wait</B>

 <B CLASS="Keyword">

until</B>

 Clk_x_2 = '1';</P>

<P CLASS="Computer">

<A NAME="pgfId=274842">

 </A>

		<B CLASS="Keyword">

case</B>

 (Phase) <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=274843">

 </A>

		<B CLASS="Keyword">

when</B>

 '0' =&gt; Phase &lt;= '1'; <B CLASS="Keyword">

when</B>

 <B CLASS="Keyword">

others</B>

 =&gt; Phase &lt;= '0';</P>

<P CLASS="Computer">

<A NAME="pgfId=274844">

 </A>

		<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

case</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=274845">

 </A>

<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

process</B>

;</P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=274846">

 </A>

12.14&nbsp;(VHDL and process sensitivity list, 15  min.) Simulate the following code with the test input vectors shown:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=274847">

 </A>

<B CLASS="Keyword">

entity</B>

 AND2 <B CLASS="Keyword">

is port</B>

 (a, b <B CLASS="Keyword">

in</B>

 : BIT; c <B CLASS="Keyword">

out</B>

 : BIT); <B CLASS="Keyword">

end</B>

 AND2;</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=274848">

 </A>

<B CLASS="Keyword">

architecture</B>

 Bad_behavior <B CLASS="Keyword">

of</B>

 AND2 <B CLASS="Keyword">

is begin</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=274849">

 </A>

	test inputs: (a b) = (1 1) (0 1) (0 0) (1 0) (1 1)</P>

<P CLASS="Computer">

<A NAME="pgfId=274850">

 </A>

	<B CLASS="Keyword">

process</B>

 (a) <B CLASS="Keyword">

begin </B>

c &lt;= a <B CLASS="Keyword">

and</B>

 b; <B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

process</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=274851">

 </A>

<B CLASS="Keyword">

end</B>

;</P>

<P CLASS="ExerciseNoIndent">

<A NAME="pgfId=274852">

 </A>

Now try to synthesize this code. Do you get an error message? If not, try simulating the synthesized logic and compare with your earlier simulation results.</P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=274912">

 </A>

12.15&nbsp;(MUX logic, 20  min.) Synthesize the following VHDL:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=274913">

 </A>

<B CLASS="Keyword">

entity</B>

 MuxLogic <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=274914">

 </A>

	<B CLASS="Keyword">

port</B>

 (InBus : <B CLASS="Keyword">

in</B>

 BIT_VECTOR(3 <B CLASS="Keyword">

downto</B>

 0);</P>

<P CLASS="Computer">

<A NAME="pgfId=274915">

 </A>

	Sel : <B CLASS="Keyword">

in</B>

 BIT_VECTOR(1 <B CLASS="Keyword">

downto</B>

 0);</P>

<P CLASS="Computer">

<A NAME="pgfId=274916">

 </A>

	OutBit : <B CLASS="Keyword">

out</B>

 BIT);</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=274917">

 </A>

<B CLASS="Keyword">

end</B>

 MuxLogic;</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=274918">

 </A>

<B CLASS="Keyword">

architecture</B>

 Synthesis_1 <B CLASS="Keyword">

of</B>

 MuxLogic <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=274919">

 </A>

	<B CLASS="Keyword">

begin</B>

 <B CLASS="Keyword">

process </B>

(Sel, InBus)</P>

<P CLASS="Computer">

<A NAME="pgfId=274920">

 </A>

	<B CLASS="Keyword">

begin</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=274921">

 </A>

		<B CLASS="Keyword">

case</B>

 Sel <B CLASS="Keyword">

is</B>

</P>

<P CLASS="Computer">

<A NAME="pgfId=274922">

 </A>

		<B CLASS="Keyword">

when</B>

 &quot;00&quot; =&gt; OutBit &lt;= <B CLASS="Keyword">

not</B>

(InBus(0));</P>

<P CLASS="Computer">

<A NAME="pgfId=274923">

 </A>

		<B CLASS="Keyword">

when</B>

 &quot;01&quot; =&gt; OutBit &lt;= InBus(1) <B CLASS="Keyword">

and</B>

 InBus(2);</P>

<P CLASS="Computer">

<A NAME="pgfId=274924">

 </A>

		<B CLASS="Keyword">

when</B>

 &quot;10&quot; =&gt; OutBit &lt;= InBus(2) <B CLASS="Keyword">

or</B>

 InBus(1);</P>

<P CLASS="Computer">

<A NAME="pgfId=274925">

 </A>

		<B CLASS="Keyword">

when</B>

 &quot;11&quot; =&gt; OutBit &lt;= InBus(3) <B CLASS="Keyword">

xor</B>

 InBus(0);</P>

<P CLASS="Computer">

<A NAME="pgfId=274926">

 </A>

		<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

case</B>

;</P>

<P CLASS="Computer">

<A NAME="pgfId=274927">

 </A>

	<B CLASS="Keyword">

end</B>

 <B CLASS="Keyword">

process</B>

;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=274928">

 </A>

<B CLASS="Keyword">

end</B>

 Synthesis_1;</P>

<P CLASS="ExerciseNoIndent">

<A NAME="pgfId=274929">

 </A>

Does the synthesizer implement the <SPAN CLASS="BodyComputer">

case</SPAN>

 statement using a MUX? Explain your answer carefully by using the synthesis reports and the synthesized netlist. Try synthesizing again with minimum-area constraint and then maximum-speed constraint. Does this alter the implementation chosen by the synthesis tool? Explain.</P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=274930">

 </A>

12.16&nbsp;(Arithmetic overflow in VHDL) Synthesize the following model (you will need arithmetic packages):</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=274931">

 </A>

<B CLASS="Keyword">

entity</B>

 Adder1 <B CLASS="Keyword">

is port</B>

 (InBusA,</P>

<P CLASS="Computer">

<A NAME="pgfId=274932">

 </A>

	InBusB : <B CLASS="Keyword">

in</B>

  Std_logic_vector(3 <B CLASS="Keyword">

downto</B>

 0);</P>

<P CLASS="Computer">

<A NAME="pgfId=274933">

 </A>

	OutBus : <B CLASS="Keyword">

out</B>

 Std_logic_vector(3 <B CLASS="Keyword">

downto</B>

 0));</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=274934">

 </A>

<B CLASS="Keyword">

end</B>

 Adder1;</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=274935">

 </A>

<B CLASS="Keyword">

architecture</B>

 Behavior <B CLASS="Keyword">

of</B>

 Adder1 <B CLASS="Keyword">

is begin </B>

OutBus &lt;= InBusA + InBusB;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=274936">

 </A>

<B CLASS="Keyword">

end</B>

 Behavior;</P>

<P CLASS="Exercise">

<A NAME="pgfId=274937">

 </A>

Repeat the synthesis with the following modification and explain the difference: </P>

<P CLASS="ComputerOneLine">

<A NAME="pgfId=274938">

 </A>

OutBus : <B CLASS="Keyword">

out</B>

 Std_logic_vector(4 <B CLASS="Keyword">

downto</B>

 0));</P>

<P CLASS="Exercise">

<A NAME="pgfId=274939">

 </A>

Finally, make the following additional modification and explain all your results:</P>

<P CLASS="ComputerOneLine">

<A NAME="pgfId=274940">

 </A>

OutBus &lt;= ( &quot;0&quot; &amp; InBusA) + (&quot;0&quot; &amp;  InBusB) ;</P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=275774">

 </A>

12.17&nbsp;(Verilog integers, 30  min.) Consider the following Verilog module:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=275775">

 </A>

<B CLASS="Keyword">

module</B>

 TestIntegers (clk, out)</P>

<P CLASS="Computer">

<A NAME="pgfId=275776">

 </A>

	<B CLASS="Keyword">

integer</B>

 i; <B CLASS="Keyword">

reg</B>

 [1:0] out; <B CLASS="Keyword">

input</B>

 clk; <B CLASS="Keyword">

output</B>

 out;</P>

<P CLASS="Computer">

<A NAME="pgfId=275777">

 </A>

	<B CLASS="Keyword">

always</B>

 @(<B CLASS="Keyword">

posedge</B>

 clk) <B CLASS="Keyword">

begin</B>

 i = i + 1; out = i; <B CLASS="Keyword">

end</B>

</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=275778">

 </A>

<B CLASS="Keyword">

endmodule</B>

 </P>

<P CLASS="ExerciseNoIndent">

<A NAME="pgfId=275779">

 </A>

Write a test module for <SPAN CLASS="BodyComputer">

TestIntegers</SPAN>

 and simulate the behavior. Try to synthesize <SPAN CLASS="BodyComputer">

TestIntegers</SPAN>

 and explain what happens.</P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=275992">

 </A>

12.18&nbsp;<A NAME="36136">

 </A>

(Verilog shift register, 30  min.) Consider this code for a shift register:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=275993">

 </A>

<B CLASS="Keyword">

module</B>

 Shift1 (clk, q0, q1, q2)</P>

<P CLASS="Computer">

<A NAME="pgfId=275994">

 </A>

	<B CLASS="Keyword">

input</B>

 clk, q0; <B CLASS="Keyword">

output</B>

 q2, q1; <B CLASS="Keyword">

reg</B>

 q2, q1;</P>

<P CLASS="Computer">

<A NAME="pgfId=275995">

 </A>

	<B CLASS="Keyword">

always</B>

 (@ <B CLASS="Keyword">

posedge</B>

 clk) q1 = q0; <B CLASS="Keyword">

always</B>

 (@ <B CLASS="Keyword">

posedge</B>

 clk) q2 = q1;</P>

<P CLASS="ComputerLast">

<A NAME="pgfId=275996">

 </A>

<B CLASS="Keyword">

endmodule</B>

 </P>

<P CLASS="Exercise">

<A NAME="pgfId=275997">

 </A>

Write a module <SPAN CLASS="BodyComputer">

Test</SPAN>

 to exercise this module. Does it simulate correctly? Can you synthesize your code for <SPAN CLASS="BodyComputer">

Shift1</SPAN>

 as it is? Change the body of the code as follows (call this module <SPAN CLASS="BodyComputer">

Shift2</SPAN>

):</P>

<P CLASS="ComputerOneLine">

<A NAME="pgfId=275998">

 </A>

<B CLASS="Keyword">

	always</B>

 (@ <B CLASS="Keyword">

posedge</B>

 clk) q1 = #1 q0; <B CLASS="Keyword">

always</B>

 (@ <B CLASS="Keyword">

posedge</B>

 clk) q2 = #1 q1;</P>

<P CLASS="Exercise">

<A NAME="pgfId=275999">

 </A>

Does this simulate correctly? Now change the code as follows (<SPAN CLASS="BodyComputer">

Shift3</SPAN>

):</P>

<P CLASS="ComputerOneLine">

<A NAME="pgfId=276000">

 </A>

	<B CLASS="Keyword">

always</B>

 (@ <B CLASS="Keyword">

posedge</B>

 clk) <B CLASS="Keyword">

begin </B>

q1 = q0; q2 = q1; <B CLASS="Keyword">

end</B>

 </P>

<P CLASS="Exercise">

<A NAME="pgfId=276001">

 </A>

Does this simulate correctly? Can you synthesize <SPAN CLASS="BodyComputer">

Shift3</SPAN>

? Finally, change the code to the following (<SPAN CLASS="BodyComputer">

Shift4</SPAN>

):</P>

<P CLASS="ComputerOneLine">

<A NAME="pgfId=276002">

 </A>

	<B CLASS="Keyword">

always</B>

 (@ <B CLASS="Keyword">

posedge</B>

 clk) q1 &lt;= q0; <B CLASS="Keyword">

always</B>

 (@ <B CLASS="Keyword">

posedge</B>

 clk) q2 &lt;= q1</P>

<P CLASS="Exercise">

<A NAME="pgfId=276003">

 </A>

Does this simulate correctly? Can you synthesize <SPAN CLASS="BodyComputer">

Shift4</SPAN>

?</P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=276412">

 </A>

12.19&nbsp;(Reset, 20  min.) Use simulation results to explain the difference between:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=276413">

 </A>

<B CLASS="Keyword">

always</B>

 (@<B CLASS="Keyword">

posedge</B>

 clk) <B CLASS="Keyword">

if</B>

(clr) Q = 0; </P>

<P CLASS="ComputerLast">

<A NAME="pgfId=394102">

 </A>

<B CLASS="Keyword">

always</B>

 (@<B CLASS="Keyword">

posedge</B>

 clk) <B CLASS="Keyword">

if</B>

(rst) Q = 1;</P>

<P CLASS="Exercise">

<A NAME="pgfId=276414">

 </A>

and</P>

<P CLASS="ComputerOneLine">

<A NAME="pgfId=276415">

 </A>

<B CLASS="Keyword">

always</B>

 (@ <B CLASS="Keyword">

posedge</B>

 clk) <B CLASS="Keyword">

begin if</B>

 (clr) Q = 0; <B CLASS="Keyword">

if</B>

 (rst) Q = 1; <B CLASS="Keyword">

end</B>

 </P>

<P CLASS="ExerciseHead">

<A NAME="pgfId=276426">

 </A>

12.20&nbsp;(Verilog assignments, 30  min.) Consider the following Verilog module:</P>

<P CLASS="ComputerFirst">

<A NAME="pgfId=276427">

 </A>

<B CLASS="Keyword">

module</B>

 TestAssign1(sel) <B CLASS="Keyword">

input</B>

 sel; <B CLASS="Keyword">

reg </B>

outp; </P>

<P CLASS="Computer">

<A NAME="pgfId=276428">

 </A>

	<SPAN CLASS="Bold">

always</SPAN>

 @sel <SPAN CLASS="Bold">

begin</SPAN>

 outp &lt;= 1; <B CLASS="Keyword">

if</B>
1234

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