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<H1 CLASS="Heading1">
<A NAME="pgfId=273376">
</A>
12.14 <A NAME="27818">
</A>
Problems</H1>
<P CLASS="Exercise">
<A NAME="pgfId=273377">
</A>
* = Difficult, ** = Very difficult, *** = Extremely difficult</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=273523">
</A>
12.1 (Comparator/MUX)</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=395113">
</A>
a. (30 min.) Build a DesignWorks (or use another tool) model for the schematic in <A HREF="CH12.1.htm#40122" CLASS="XRef">
Figure 12.1</A>
and simulate the operation of this circuit to check that it performs the same function as the Verilog code. <SPAN CLASS="Emphasis">
Hint:</SPAN>
You could also use VeriWell to simulate the Verilog netlist.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=395137">
</A>
b. (30 min.) Simulate the schematic (or the Verilog netlist) shown in <A HREF="CH12.2.htm#22754" CLASS="XRef">
Figure 12.2</A>
and check that it performs the comparator/MUX function correctly.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=395162">
</A>
c. (30 min.) Simulate the schematic (or the Verilog netlist) of <A HREF="CH12.2.htm#16015" CLASS="XRef">
Figure 12.3</A>
. If you have access to a logic synthesizer and cell library, you might resynthesize the comparator/MUX and compare the results with those shown in Figures <A HREF="CH12.2.htm#22754" CLASS="XRef">
12.2</A>
and <A HREF="CH12.2.htm#16015" CLASS="XRef">
12.3</A>
.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=395181">
</A>
d. (20 min.) Build a schematic (or Verilog model) for macro <SPAN CLASS="BodyComputer">
cm8</SPAN>
in <A HREF="CH12.2.htm#27840" CLASS="XRef">
Figure 12.4</A>
.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=395243">
</A>
e. (30 min.) Simulate the schematic (or Verilog netlist) shown in <A HREF="CH12.2.htm#27840" CLASS="XRef">
Figure 12.4</A>
.</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=395112">
</A>
12.2 (*Verilog assignments, 15 min.) Simulate and test the following model paying attention to initialization. Attempt to synthesize it. Explain your results.</P>
<P CLASS="Computer">
<A NAME="pgfId=273524">
</A>
<B CLASS="Keyword">
module</B>
dff (D, Q, Clk, Rst);</P>
<P CLASS="Computer">
<A NAME="pgfId=273525">
</A>
<B CLASS="Keyword">
parameter</B>
width = 1, reset_value = 0; <B CLASS="Keyword">
input</B>
[width - 1 : 0] D;</P>
<P CLASS="Computer">
<A NAME="pgfId=273526">
</A>
<B CLASS="Keyword">
output</B>
[width - 1 : 0] Q; <B CLASS="Keyword">
reg</B>
[width - 1 : 0] Q; <B CLASS="Keyword">
input</B>
Clk,Rst;</P>
<P CLASS="Computer">
<A NAME="pgfId=273527">
</A>
<B CLASS="Keyword">
initial</B>
Q = {width{1'bx}};</P>
<P CLASS="Computer">
<A NAME="pgfId=273528">
</A>
<B CLASS="Keyword">
always</B>
@ ( <B CLASS="Keyword">
posedge</B>
Clk <B CLASS="Keyword">
or</B>
<B CLASS="Keyword">
negedge</B>
Rst )</P>
<P CLASS="Computer">
<A NAME="pgfId=273529">
</A>
<B CLASS="Keyword">
if</B>
( Rst == 0 ) Q <= #1 reset_value; <B CLASS="Keyword">
else</B>
Q <= #1 D;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=273530">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=273551">
</A>
12.3 (Digital filter) (30 min.) Write HDL code to model the following filter:</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=273552">
</A>
y0 <= c(0) *<SPAN CLASS="Symbol">
</SPAN>
x(0) + c(1) * x(1) + b(2) * x(2) ;</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=273553">
</A>
Use <SPAN CLASS="BodyComputer">
c(0) = -4</SPAN>
, <SPAN CLASS="BodyComputer">
c(0) = +5</SPAN>
, <SPAN CLASS="BodyComputer">
c(0) = -3</SPAN>
, but make your code flexible so that these coefficients may be changed. (120 min.) Simulate, test, and synthesize your model. <SPAN CLASS="Emphasis">
Hint:</SPAN>
You should use the transfer equation in your code (Verilog or VHDL).</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=295140">
</A>
12.4 <A NAME="38579">
</A>
(Hand design, 60 min.) Use hand calculation and gate delay values obtained from a data book to estimate the critical path of the comparator/MUX shown in <A HREF="CH12.1.htm#40122" CLASS="XRef">
Figure 12.1</A>
. Assume the critical path (the one with the longest delay) is from the <SPAN CLASS="BodyComputer">
a[2]</SPAN>
input (the input with the largest load) -> XOR -> inverter -> four-input NAND -> three-input OR -> select input of two-input MUX (the symbol -> means “through the”). You will need to find the t<SUB CLASS="Subscript">
PHL</SUB>
(falling) and t<SUB CLASS="Subscript">
PLH</SUB>
(rising) propagation delays for each gate used in the critical path. Do not adjust the delays for the loading (fanout) at the output of each gate on the critical path, assume a loading equal to one input of a two-input NAND gate. Change the AND–NOR gate combination to a NAND–NAND gate combination and recalculate the critical path delay. </P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=295148">
</A>
12.5 (Critical path, 30 min.) Enter the schematic shown in <A HREF="CH12.1.htm#40122" CLASS="XRef">
Figure 12.1</A>
and, using a gate-level simulator or a timing analyzer, obtain the delays from the <SPAN CLASS="BodyComputer">
a</SPAN>
and <SPAN CLASS="BodyComputer">
b</SPAN>
inputs to the outputs. What is the critical path?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=273926">
</A>
12.6 <A NAME="41098">
</A>
(Verilog sensitivity list, 30 min.) Simulate the following Verilog module with the test pattern shown and explain your results.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=273927">
</A>
<B CLASS="Keyword">
module</B>
and2_bad(a, b, c); <B CLASS="Keyword">
input</B>
a, b; <B CLASS="Keyword">
output</B>
c; <B CLASS="Keyword">
reg</B>
c;</P>
<P CLASS="Computer">
<A NAME="pgfId=273928">
</A>
// test pattern: (a b) = (1 1) (0 1) (0 0) (1 0) (1 1) </P>
<P CLASS="Computer">
<A NAME="pgfId=273935">
</A>
<B CLASS="Keyword">
always</B>
@(a) c <= a & b;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=273936">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="Exercise">
<A NAME="pgfId=273937">
</A>
Can you synthesize this module as it is? What is the error message if you get one? If you can synthesize this module as it is, simulate the synthesized logic and compare the output with the Verilog simulation.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=274003">
</A>
12.7 <A NAME="31514">
</A>
(Verilog decoder, 30 min.) Synthesize the following Verilog module with minimum-area constraint and then with maximum-speed constraint. Compare the resulting logic in each case.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=274004">
</A>
<B CLASS="Keyword">
module</B>
Decoder4_to_16(Enable, In_4, Out_16); </P>
<P CLASS="Computer">
<A NAME="pgfId=274005">
</A>
<B CLASS="Keyword">
input</B>
Enable; <B CLASS="Keyword">
input</B>
[3:0] In_4; <B CLASS="Keyword">
output</B>
[15:0] Out_16;</P>
<P CLASS="Computer">
<A NAME="pgfId=274006">
</A>
<B CLASS="Keyword">
reg</B>
[15:0] Out_16;</P>
<P CLASS="Computer">
<A NAME="pgfId=274007">
</A>
<B CLASS="Keyword">
always</B>
@(Enable <B CLASS="Keyword">
or</B>
In_4)</P>
<P CLASS="Computer">
<A NAME="pgfId=274008">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=274009">
</A>
Out_16 = 16'hzzzz;</P>
<P CLASS="Computer">
<A NAME="pgfId=274010">
</A>
<B CLASS="Keyword">
if</B>
(Enable == 1) <B CLASS="Keyword">
begin </B>
Out_16 = 16'h0000; Out_16[In_4] = 1; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=274011">
</A>
<B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=274012">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="Exercise">
<A NAME="pgfId=330471">
</A>
What happens if you change the <SPAN CLASS="BodyComputer">
if</SPAN>
statement to <SPAN CLASS="BodyComputer">
if (Enable === 1)</SPAN>
?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=274121">
</A>
12.8 <A NAME="40819">
</A>
(Verilog eight-input MUX, 20 min.) Synthesize the following code with maximum-speed constraint and then minimum-area constraint. Compare the results.</P>
<P CLASS="Computer">
<A NAME="pgfId=274122">
</A>
<B CLASS="Keyword">
module</B>
Mux8_to_1(InBus, Select, OutEnable, OutBit);</P>
<P CLASS="Computer">
<A NAME="pgfId=274123">
</A>
<B CLASS="Keyword">
input</B>
[7:0] InBus; <B CLASS="Keyword">
input</B>
[2:0] Select; <B CLASS="Keyword">
input</B>
OutEnable; </P>
<P CLASS="Computer">
<A NAME="pgfId=274124">
</A>
<B CLASS="Keyword">
output</B>
OutBit; <B CLASS="Keyword">
reg</B>
OutBit;</P>
<P CLASS="Computer">
<A NAME="pgfId=274125">
</A>
<B CLASS="Keyword">
always</B>
@(OutEnable <B CLASS="Keyword">
or</B>
Select <B CLASS="Keyword">
or</B>
InBus)</P>
<P CLASS="Computer">
<A NAME="pgfId=274126">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=274127">
</A>
<B CLASS="Keyword">
if</B>
(OutEnable == 1) OutBit = InBus[Select]; <B CLASS="Keyword">
else</B>
OutBit = 1'bz;</P>
<P CLASS="Computer">
<A NAME="pgfId=274128">
</A>
<B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=274129">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=274230">
</A>
12.9 <A NAME="39136">
</A>
(Verilog parity generator, 30 min.) Synthesize the following code with maximum-speed constraint and then minimum-area constraint. Compare the results.</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=274231">
</A>
<B CLASS="Keyword">
module</B>
Parity (BusIn, ParityB); </P>
<P CLASS="Computer">
<A NAME="pgfId=274232">
</A>
<B CLASS="Keyword">
input</B>
[8:0] BusIn; <B CLASS="Keyword">
output</B>
ParityB; <B CLASS="Keyword">
reg</B>
ParityB;</P>
<P CLASS="Computer">
<A NAME="pgfId=274233">
</A>
<B CLASS="Keyword">
always</B>
@(BusIn) <B CLASS="Keyword">
if</B>
(^Busin == 0 ) ParityB = 1; <B CLASS="Keyword">
else</B>
ParityB = 0;</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=274234">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=274277">
</A>
12.10 (Verilog edges and levels, 30 min.) What is the function of the following model? List the cells produced by a logic synthesizer, their function, and an explanation of why they were synthesized.</P>
<P CLASS="Computer">
<A NAME="pgfId=274278">
</A>
<B CLASS="Keyword">
module</B>
DD(D, C, R, Q, QB); <B CLASS="Keyword">
input</B>
D, C, R; <B CLASS="Keyword">
output</B>
Q, QB; <B CLASS="Keyword">
reg</B>
Q, QB, L;</P>
<P CLASS="Computer">
<A NAME="pgfId=274279">
</A>
<B CLASS="Keyword">
always</B>
@(<B CLASS="Keyword">
posedge</B>
C <B CLASS="Keyword">
or</B>
<B CLASS="Keyword">
posedge</B>
R) <B CLASS="Keyword">
if</B>
(R == 1) L = 0; <B CLASS="Keyword">
else</B>
L = D;</P>
<P CLASS="Computer">
<A NAME="pgfId=274280">
</A>
<B CLASS="Keyword">
always</B>
@(L) <B CLASS="Keyword">
begin</B>
Q = L; QB = ~L; <B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=274281">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=274467">
</A>
12.11 <A NAME="12699">
</A>
(Verilog adders, 120 min.) Synthesize the following code with maximum-speed constraint and then minimum-area constraint. What type of adder architecture does the synthesis tool produce in each case (ripple-carry, lookahead, etc.)? Show exactly how you reached your conclusion. If you can, use either synthesis tool directives, shell commands, or standard components (Synopsys <A NAME="marker=395402">
</A>
DesignWare or Xilinx <A NAME="marker=395403">
</A>
X-BLOX, for example) to direct the synthesis tool to a specific adder implementation. Check that when you optimize the synthesized logic the adder architecture is not broken up. Next, if you can, find a way to make the synthesis tool break up the adder and reoptimize the logic. Does anything change?</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=274468">
</A>
<B CLASS="Keyword">
module</B>
adder1(a, a, outp);</P>
<P CLASS="Computer">
<A NAME="pgfId=274469">
</A>
<B CLASS="Keyword">
input</B>
[3:0] a; <B CLASS="Keyword">
input</B>
[3:0] b; <B CLASS="Keyword">
output</B>
[3:0] outp; <B CLASS="Keyword">
reg</B>
[3:0] outp;</P>
<P CLASS="Computer">
<A NAME="pgfId=274470">
</A>
// if you can, change the next line to drive your synthesis tool</P>
<P CLASS="Computer">
<A NAME="pgfId=274471">
</A>
// pragma|compass|synopsys|whatever max_delay constraint</P>
<P CLASS="Computer">
<A NAME="pgfId=306767">
</A>
<B CLASS="Keyword">
begin</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=306768">
</A>
outp <= a + b; // Map me to DesignWare, X-Blox etc., if you can.</P>
<P CLASS="Computer">
<A NAME="pgfId=306769">
</A>
<B CLASS="Keyword">
end</B>
</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=274475">
</A>
<B CLASS="Keyword">
endmodule</B>
</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=274819">
</A>
12.12 <A NAME="34209">
</A>
(Elementary gates in Verilog, 60 min.) Synthesize and optimize the following (you will have to write some more code to go around these statements):</P>
<P CLASS="ComputerOneLine">
<A NAME="pgfId=274820">
</A>
And3 = &{In1,In2,In3}; Or3 = |{In1,In2,In3}; Xor3 = ^{In1,In2,In3};</P>
<P CLASS="ExerciseNoIndent">
<A NAME="pgfId=274821">
</A>
This should produce three-input AND, OR, and XOR gates. Now synthesize and optimize eight-input AND, OR, and XOR gates in the same way with minimum-area constraint and then maximum-speed constraint. Compare your results. How and why do the synthesis results and your answers change if you place a large capacitive load on the outputs. <SPAN CLASS="Emphasis">
Hint:</SPAN>
Try a load equivalent to 16 minimum-size inverters. Can you explain these results using logical effort?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=274834">
</A>
12.13 (Synthesizable VHDL, 20 min.) Complete the following code fragment and try to synthesize the VHDL:</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=274835">
</A>
<B CLASS="Keyword">
process begin</B>
</P>
<P CLASS="Computer">
<A NAME="pgfId=274836">
</A>
<B CLASS="Keyword">
wait</B>
<B CLASS="Keyword">
until</B>
Clk = '1';</P>
<P CLASS="Computer">
<A NAME="pgfId=274837">
</A>
Phase <= "0" <B CLASS="Keyword">
after</B>
0 ns; Phase <= "1" <B CLASS="Keyword">
after</B>
10 ns; </P>
<P CLASS="ComputerLast">
<A NAME="pgfId=274838">
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