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<TITLE> VERILOG HDL RESOURCES </TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
<P>[ <A HREF="../../ASICs.htm#anchor749424">Chapter Index</A> ] [ <A HREF="APP2.1.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
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<H1 CLASS="zAppChapterTitle">
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VERILOG HDL <BR>
RESOURCES</H1>
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The definitive reference for the Verilog HDL is IEEE Std 1364-1995. This standard is known as the <SPAN CLASS="Definition">
IEEE Verilog® HDL language reference manual</SPAN>
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(<SPAN CLASS="Definition">
LRM</SPAN>
) and the 1995 version is referred to here as the <A NAME="marker=58743">
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95 LRM <A NAME="[IEEE 1364-1995]">
</A>
[IEEE 1364-1995].<A HREF="#pgfId=43845" CLASS="footnote">
1</A>
Verilog is a registered trademark of Cadence Design Systems and <A NAME="marker=58744">
</A>
Verilog-XL is a commercial simulator. </P>
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B.1 Explanation of the Verilog HDL BNF</A>
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B.2 Verilog HDL Syntax</A>
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B.3 BNF Index</A>
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B.4 Verilog HDL LRM</A>
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B.5 Bibliography</A>
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B.6 References</A>
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<DIV CLASS="footnotes">
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1.</SPAN>
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IEEE Std 1364-1995, Copyright © 1995. IEEE. All rights reserved. The Verilog HDL syntax section in this appendix is reprinted from the IEEE copyright material with permission.</P>
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