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<H1 CLASS="zAppHeading1">
<A NAME="pgfId=25646">
</A>
B.5 Bibliography</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=58312">
</A>
There are fewer books available on Verilog than on VHDL. The best reference book is the IEEE Verilog HDL LRM <A NAME="[IEEE 1364-1995]b">
</A>
[IEEE 1364-1995]; it is detailed as well as containing many examples. In addition to the references given in Chapter 11, the following books concentrate on Verilog: Sternheim, Singh, and Trivedi <A NAME="[Sternheim, Singh, and Trivedi, 1990]">
</A>
[1990] (Yatin Trivedi was the technical editor for the 95 LRM); Thomas and Moorby <A NAME="[Thomas and Moorby, 1991]">
</A>
[1991]; Smith <A NAME="[Smith, 1996]">
</A>
[1996]; and Golze and Blinzer <A NAME="[Golze and Blinzer, 1996]">
</A>
[1996]. Capilano Computing Systems has produced a book to accompany its Verilog Modeler product <A NAME="[Capilano, 1997]">
</A>
[Capilano, 1997].</P>
<P CLASS="zAppBody">
<A NAME="pgfId=58259">
</A>
Sandstrom compiled an interesting cross-reference between Verilog and VHDL (a 2.5 page table listing the correspondence between major constructs in both languages) in a pull-out supplement to <SPAN CLASS="Emphasis">
Integrated System Design Magazine</SPAN>
<A NAME="marker=58673">
</A>
. An electronic version of this article is at <SPAN CLASS="URL">
<A HREF="http://www.isdmag.com" CLASS="URL">
http://www.isdmag.com</A>
</SPAN>
<SPAN CLASS="BodyComputer">
</SPAN>
(the article is labeled January 1996, but filed under October 1995). Other online articles related to Verilog at <SPAN CLASS="BodyComputer">
www.isdmag.com </SPAN>
, include case studies of Sun Microsystems’ ULTRASparc-1 (June 1996) and Hewlett–Packard’s PA-8000 (January, February, and March 1997); both CPUs were designed with Verilog behavioral models. The March 1997 issue also contains an article on the recent history and the future plans of Open Verilog International (<A NAME="marker=58674">
</A>
OVI). OVI helped create IEEE Std 1364-1995 and sponsored the annual <SPAN CLASS="Emphasis">
International Verilog HDL Conference</SPAN>
<A NAME="marker=58675">
</A>
(IVC). In 1997 the IVC merged with the <A NAME="marker=58688">
</A>
VHDL International Users’ Forum (<A NAME="marker=58689">
</A>
VIUF<A NAME="marker=58690">
</A>
) to form the <SPAN CLASS="Emphasis">
IVC/VIUF Conference</SPAN>
<A NAME="marker=58691">
</A>
(see <SPAN CLASS="URL">
<A HREF="http://www.hdlcon.org" CLASS="URL">
http://www.hdlcon.org</A>
</SPAN>
).</P>
<P CLASS="zAppBody">
<A NAME="pgfId=57716">
</A>
In January of 1995 OVI reactivated the <A NAME="marker=58694">
</A>
Technical Coordinating Committee (<A NAME="marker=58695">
</A>
TCC) to recommend updates and changes to Verilog HDL. The TCC comprises <A NAME="marker=58696">
</A>
technical subcommittees (<A NAME="marker=58697">
</A>
TSC), which are developing a delay calculator standard (<A NAME="marker=58698">
</A>
LM-TSC), analog extensions to Verilog HDL (<A NAME="marker=58702">
</A>
VA-TSC), an ASIC library modeling standard (<A NAME="marker=58701">
</A>
PS-TSC), cycle-based simulation standard (<A NAME="marker=58699">
</A>
VC-TSC), timing-constraint formats (<A NAME="marker=58703">
</A>
VS-TSC), as well as Verilog language enhancements and extensions (<A NAME="marker=58700">
</A>
VD-TSC). Links and information about OVI are available at <SPAN CLASS="URL">
<A HREF="http://www.avanticorp.com" CLASS="URL">
http://www.avanticorp.com</A>
</SPAN>
and <SPAN CLASS="URL">
<A HREF="http://www.chronologic.com" CLASS="URL">
http://www.chronologic.com </A>
</SPAN>
. The OVI web site is <SPAN CLASS="URL">
<A HREF="http://www.verilog.org/ovi" CLASS="URL">
http://www.verilog.org/ovi</A>
</SPAN>
. Information on the activities of the OVI committees is available at the Meta-Software site, <SPAN CLASS="URL">
<A HREF="ftp://ftp.metasw.com/pub" CLASS="URL">
ftp://ftp.metasw.com/pub</A>
</SPAN>
. </P>
<P CLASS="zAppBody">
<A NAME="pgfId=58126">
</A>
The work of the OVI and IEEE groups is related. For example, the <A NAME="marker=58704">
</A>
IEEE Design Automation Standards Committee (<A NAME="marker=58705">
</A>
DASC) contains the <A NAME="marker=58706">
</A>
Verilog Working Group (<A NAME="marker=58707">
</A>
PAR 1364), the <A NAME="marker=58708">
</A>
Circuit Delay and Power Calculation (<A NAME="marker=58709">
</A>
DPC) System Study Group (<A NAME="marker=58710">
</A>
P1481), as well as the VHDL and other WGs. Thus, the OVI DC-TSC directory contains the <A NAME="marker=58711">
</A>
Standard Delay Calculation System (<A NAME="marker=58712">
</A>
DCS) Specification (v1.0) approved by OVI/CFI and currently being studied by the IEEE DPC Study Group. DCS provides a standard system for designers to calculate chip delay and power using the following methods: <A NAME="marker=58713">
</A>
Delay Calculation Language (<A NAME="marker=58714">
</A>
DCL) from IBM and CFI, <A NAME="marker=58715">
</A>
Detailed Standard Parasitic Format (<A NAME="marker=58716">
</A>
DSPF) and <A NAME="marker=58717">
</A>
Reduced Standard Parasitic Format (<A NAME="marker=58718">
</A>
RSPF) from Cadence Design Systems (combined into a new <A NAME="marker=58719">
</A>
Standard Parasitics Exchange Format, <A NAME="marker=58720">
</A>
SPEF), and <A NAME="marker=58721">
</A>
Physical Design Exchange Format (<A NAME="marker=58722">
</A>
PDEF) from Synopsys. The current IEEE standardization work is expanding the scope to add power calculation. Thus, useful information relating to Verilog may be found at the VHDL site, <A NAME="marker=58723">
</A>
VIUF Internet Services (<A NAME="marker=58724">
</A>
VIIS at <SPAN CLASS="URL">
<A HREF="http://www.vhdl.org" CLASS="URL">
http://www.vhdl.org</A>
</SPAN>
), as well as the OVI site.</P>
<P CLASS="zAppBody">
<A NAME="pgfId=60641">
</A>
Two <SPAN CLASS="BodyComputer">
usenet</SPAN>
newsgroups are related to Verilog: <SPAN CLASS="BodyComputer">
comp.lang.verilog</SPAN>
<A NAME="marker=60639">
</A>
and <SPAN CLASS="BodyComputer">
comp.cad.synthesis </SPAN>
<A NAME="marker=60640">
</A>
. In January of 1997 the Verilog news archive was lost due to a disk problem. While attempts are made to restore the archive, the <A NAME="marker=60642">
</A>
Verilog Frequently Asked Questions (FAQ) list is still available at <SPAN CLASS="URL">
<A HREF="http://www.lib.ox.ac.uk/internet/news/faq/archive/verilog-faq.html" CLASS="URL">
http://www.lib.ox.ac.uk/internet/news/faq/archive/verilog-faq.html</A>
</SPAN>
. A list of CAD-related newsgroups (including <SPAN CLASS="BodyComputer">
comp.lang.verilog</SPAN>
) is maintained at Sun Microsystems’ <A NAME="marker=60643">
</A>
DACafe (<SPAN CLASS="URL">
<A HREF="http://www.ibsystems.com/DACafe/TECHNICAL/Resources/NewsGps.html" CLASS="URL">
http://www.ibsystems.com/DACafe/TECHNICAL/Resources/NewsGps.html</A>
</SPAN>
<SPAN CLASS="BodyComputer">
</SPAN>
. Sun (<SPAN CLASS="BodyComputer">
~/DACafe/USERSGROUPS</SPAN>
) also maintains the following <A NAME="marker=60644">
</A>
user groups that often discuss Verilog: Cadence, Mentor Graphics, Synopsys, VeriBest, and Viewlogic. A number of tools and resources are available on the World Wide Web, including <A NAME="marker=60645">
</A>
Verilog modes for the <A NAME="marker=60646">
</A>
emacs editor; <A NAME="marker=60647">
</A>
Verilog preprocessors in <A NAME="marker=60648">
</A>
Perl and <A NAME="marker=60649">
</A>
C (which allow the use of <SPAN CLASS="BodyComputer">
`define</SPAN>
and <SPAN CLASS="BodyComputer">
`ifdef</SPAN>
with logic synthesis tools, for example); and demonstration versions of the following simulators: <A NAME="marker=60650">
</A>
Viper from <A NAME="marker=60651">
</A>
InterHDL (<SPAN CLASS="URL">
<A HREF="http://www.interhdl.com" CLASS="URL">
http://www.interhdl.com</A>
</SPAN>
) and <A NAME="marker=60652">
</A>
VeriWell from <A NAME="marker=60653">
</A>
Wellspring Solutions (<SPAN CLASS="URL">
<A HREF="http://www.wellspring.com" CLASS="URL">
http://www.wellspring.com</A>
</SPAN>
). VeriWell now supports the Verilog PLI, including the <SPAN CLASS="BodyComputer">
acc</SPAN>
and <SPAN CLASS="BodyComputer">
tf</SPAN>
routines in IEEE Std 1364-1995 (requiring <A NAME="marker=60654">
</A>
Visual C++ 4.0 or newer for the Windows version, <A NAME="marker=60655">
</A>
Code Warrior 9 or newer for the Macintosh, and <A NAME="marker=60656">
</A>
GNU C 2.7.0 or newer for the Linux and Sparc versions). </P>
<P CLASS="zAppBody">
<A NAME="pgfId=58170">
</A>
Several personal Web pages focus on Verilog HDL; these change frequently but can be found by searching. Actel has placed a number of Verilog examples (including synthesizable code for a FIFO and a RAM) at its site: <SPAN CLASS="URL">
<A HREF="http://wwwtest.actel.com/HLD/verimain.html" CLASS="URL">
http://wwwtest.actel.com/HLD/verimain.html</A>
</SPAN>
<SPAN CLASS="BodyComputer">
</SPAN>
. Many universities maintain Web pages for Verilog-related classes. Examples are the Web site for the ee282 class at Stanford (<SPAN CLASS="URL">
<A HREF="http://lummi.Stanford.EDU/class/ee282" CLASS="URL">
http://lummi.Stanford.EDU/class/ee282</A>
</SPAN>
), which contains Verilog models for the DLX processor in the second edition of Hennessy and Patterson’s “Computer Architecture: A Quantitative Approach”; and course material for 18-360, “Introduction to Computer-Aided Digital Design,” by Prof. Don Thomas at <SPAN CLASS="URL">
<A HREF="http://www.ece.cmu.edu" CLASS="URL">
http://www.ece.cmu.edu</A>
</SPAN>
<SPAN CLASS="BodyComputer">
</SPAN>
.</P>
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