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B.6 References</H1>
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Page numbers in brackets after a reference indicate its location in the chapter body.</P>
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Capilano. 1997. <SPAN CLASS="BookTitle">
LogicWorks Verilog Modeler: Interactive Circuit Simulation Software for Windows and Macintosh.</SPAN>
Menlo Park, CA: Capilano Computing, 102 p. ISBN 0201895854. TK7888.4.L64 (as cataloged by the LOC). Addison-Wesley also gives the following additional ISBN numbers for this work: ISBN 0-201-49885-5 (Windows book and software), ISBN 0-201-49884-7 (Macintosh book and software); also available bundled with LogicWorks 3: ISBN 0-201-87436-9 (Macintosh), ISBN 0-201-87437-7 (Windows). </P>
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Golze, U., and P. Blinzer. 1996. <SPAN CLASS="BookTitle">
VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design.</SPAN>
New York: Springer, 358 p. ISBN 3540600329. TK7874.75.G65. Four pages of references. Includes a version of VeriWell from Wellsprings Solutions. </P>
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IEEE 1364-1995. <SPAN CLASS="BookTitle">
IEEE Standard Description Language Based on the Verilog® Hardware Description Language.</SPAN>
688 p. ISBN 1-55937-727-5. IEEE Ref. SH94418-NYF. Published by The IEEE, Inc., 345 East 47th Street, New York, NY 10017, USA. Inside the United States, IEEE standards may be ordered at 1-800-678-4333. See also <SPAN CLASS="URL">
<A HREF="http://www.ieee.org" CLASS="URL">
http://www.ieee.org</A>
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and<SPAN CLASS="BodyComputer">
</SPAN>
<SPAN CLASS="URL">
<A HREF="http://stdsbbs.ieee.org" CLASS="URL">
http://stdsbbs.ieee.org</A>
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. This standard was approved by the IEEE on 12 December, 1995; and approved by ANSI on 1 August, 1996 (and thus these two organizations have different publication dates). Contents: overview (4 pages); lexical conventions (8 pages); data types (13 pages); expressions (18 pages); scheduling semantics (5 pages); assignments (4 pages); gate and switch level modeling (31 pages); user-defined primitives (11 pages); behavioral modeling (26 pages); tasks and functions (6 pages); disabling of named blocks and tasks (1 page); hierarchical structures (16 pages); specify blocks (18 pages); system tasks and functions (35 pages); value change dump file (11 pages); compiler directives (8 pages); PLI TF and ACC interface mechanism (6 pages); using ACC routines (36 pages); ACC routine definitions (178 pages); using TF routines (5 pages); TF routine definitions (76 pages); using VPI routines (6 pages); VPI routine definitions (25 pages); formal syntax definition; list of keywords; system tasks and functions; compiler directives; <SPAN CLASS="BodyComputer">
acc_user.h</SPAN>
; <SPAN CLASS="BodyComputer">
veriuser.h</SPAN>
; <SPAN CLASS="BodyComputer">
vpi_user.h</SPAN>
. [<A HREF="APP2.htm#[IEEE 1364-1995]" CLASS="XRef">
reference location</A>
]</P>
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Smith, D. J. 1996. <SPAN CLASS="BookTitle">
HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL or Verilog.</SPAN>
Madison, AL: Doone Publications, 448 p. ISBN 0965193438. TK7874.6.S62. </P>
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Sternheim, E., R. Singh, and Y. Trivedi. 1990. <SPAN CLASS="BookTitle">
Digital Design with Verilog HDL.</SPAN>
Cupertino, CA: Automata Publishing, 215 p. ISBN 0962748803. TK7885.7.S74. </P>
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Thomas, D. E., and P. Moorby. 1991. <SPAN CLASS="BookTitle">
The Verilog Hardware Description Language.</SPAN>
Boston, MA: Kluwer, 223 p. ISBN 0-7923-9126-8, TK7885.7.T48 (1st ed.). ISBN 0-7923-9523-9 (2nd ed.). ISBN 0792397231 (3rd ed.). </P>
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