ch16.1.htm
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log</P>
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or 11 stages.</P>
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(16.1)</P>
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0.025 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
–12</SUP>
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The power dissipated charging the input capacitance of the flip-flop clock is <SPAN CLASS="EquationVariables">
fCV</SPAN>
<SUP CLASS="Superscript">
2</SUP>
or </P>
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<SPAN CLASS="EquationVariables">
P</SPAN>
<SUP CLASS="Superscript">
1</SUP>
<SUB CLASS="Subscript">
1</SUB>
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=</P>
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(4 <SPAN CLASS="Symbol">
¥</SPAN>
10<SUP CLASS="Superscript">
4</SUP>
) (200 MHz) (0.025 pF) (3.3 V)<SUP CLASS="Superscript">
2</SUP>
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= 2.178 W .</P>
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(16.2)</P>
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or approximately 2 W. This is only a little larger than the power dissipated driving the 800 pF clock-spine interconnect that we can calculate as follows: </P>
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P</SPAN>
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2</SUP>
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1</SUB>
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=</P>
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(200 ) (200 MHz) (20 mm) (2 pFcm<SUP CLASS="Superscript">
–1</SUP>
)(3.3 V)<SUP CLASS="Superscript">
2</SUP>
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= 1.7424 W .</P>
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(16.3)</P>
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All of this power is dissipated in the clock-driver cell. The worst problem, however, is the enormous peak current in the final inverter stage. If we assume the needed rise time is 0.1 ns (with a 200 MHz clock whose period is 5 ns), the peak current would have to approach </P>
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(800 pF) (3.3 V)</P>
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I</P>
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=</P>
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–––––––––––––</P>
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<SPAN CLASS="Symbol">
ª</SPAN>
25 A .</P>
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(16.4)</P>
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0.1 ns</P>
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Clearly such a current is not possible without extraordinary design techniques. Clock spines are used to drive loads of 100–200 pF but, as is apparent from the power dissipation problems of this example, it would be better to find a way to spread the power dissipation more evenly across the chip.</P>
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We can design a tree of clock buffers so that the taper of each stage is e ⊕ 2.7 by using a fanout of three at each node, as shown in <A HREF="CH16.1.htm#30301" CLASS="XRef">
Figure 16.17</A>
(a) and (b). The <SPAN CLASS="Definition">
clock tree</SPAN>
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, shown in <A HREF="CH16.1.htm#30301" CLASS="XRef">
Figure 16.17</A>
(c), uses the same number of stages as a clock spine, but with a lower peak current for the inverter buffers. <A HREF="CH16.1.htm#30301" CLASS="XRef">
Figure 16.17</A>
(c) illustrates that we now have another problem—we need to balance the delays through the tree carefully to minimize clock skew (see Section 17.3.1, “Clock Routing”).</P>
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FIGURE 16.17 <A NAME="30301">
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A clock tree. (a) Minimum delay is achieved when the taper of successive stages is about 3. (b) Using a fanout of three at successive nodes. (c) A clock tree for the cell-based ASIC of <A HREF="CH16.1.htm#27899" CLASS="XRef">
Figure 16.16</A>
b. We have to balance the clock arrival times at all of the leaf nodes to minimize clock skew.</P>
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Designing a clock tree that balances the rise and fall times at the leaf nodes has the beneficial side-effect of minimizing the effect of <SPAN CLASS="Definition">
hot-electron wearout</SPAN>
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. This problem occurs when an electron gains enough energy to become “hot” and jump out of the channel into the gate oxide (the problem is worse for electrons in <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel devices because electrons are more mobile than holes). The trapped electrons change the threshold voltage of the device and this alters the delay of the buffers. As the buffer delays change with time, this introduces unpredictable skew. The problem is worst when the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel device is carrying maximum current with a high voltage across the channel—this occurs during the rise-and fall-time transitions. Balancing the rise and fall times in each buffer means that they all wear out at the same rate, minimizing any additional skew.</P>
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A <SPAN CLASS="Definition">
phase-locked loop</SPAN>
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(<A NAME="marker=27609">
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PLL<A NAME="marker=83692">
</A>
) is an electronic flywheel that locks in frequency to an input clock signal. The input and output frequencies may differ in phase, however. This means that we can, for example, drive a clock network with a PLL in such a way that the output of the clock network is locked in phase to the incoming clock, thus eliminating the latency of the clock network<A NAME="[Anceau, 1982]">
</A>
. A PLL can also help to reduce random variation of the input clock frequency, known as <SPAN CLASS="Definition">
jitter</SPAN>
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, which, since it is unpredictable, must also be discounted from the time available for computation in each clock cycle. Actel was one of the first FPGA vendors to incorporate PLLs, and Actel’s online product literature explains their use in ASIC design.</P>
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1.</SPAN>
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Interconnect lengths are derived from interconnect capacitance data. Interconnect capacitance is 2 pFcm <SUP CLASS="Superscript">
–1</SUP>
.</P>
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