ch16.1.htm

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Ideally we would only need to design library pad cells for one orientation. For example, an edge pad for the south side of the chip, and a corner pad for the southeast corner. We could then generate other orientations by rotation and flipping (mirroring). Some ASIC vendors will not allow rotation or mirroring of logic cells in the mask file. To avoid these problems we may need to have separate horizontal, vertical, left-handed, and right-handed pad cells in the library with appropriate logical to physical pad mappings.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=1472">
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If we mix pad-limited and core-limited edge pads in the same pad ring, this complicates the design of corner pads. Usually the two types of edge pad cannot abut. In this case a corner pad also becomes a <A NAME="marker=1468">
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<SPAN CLASS="Definition">
pad-format changer</SPAN>
, or <A NAME="marker=1471">
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<SPAN CLASS="Definition">
hybrid corner pad</SPAN>
.</LI>
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<A NAME="pgfId=24651">
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In single-supply chips we have one VDD net and one VSS net, both <A NAME="marker=24652">
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<SPAN CLASS="Definition">
global power nets</SPAN>
. It is also possible to use <A NAME="marker=24653">
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<SPAN CLASS="Definition">
mixed power supplies</SPAN>
 (for example, 3.3 V and 5 V) or <SPAN CLASS="Definition">
multiple power supplies</SPAN>
<A NAME="marker=24656">
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 (<A NAME="marker=64323">
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digital VDD, <A NAME="marker=64324">
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analog VDD).</LI>
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<A HREF="CH16.1.htm#11801" CLASS="XRef">
Figure&nbsp;16.13</A>
(a) and (b) are magnified views of the southeast corner of our example chip and show the different types of I/O cells. <A HREF="CH16.1.htm#11801" CLASS="XRef">
Figure&nbsp;16.13</A>
(c) shows a <SPAN CLASS="Definition">
stagger-bond</SPAN>
<A NAME="marker=24635">
 </A>
 arrangement using two rows of I/O pads. In this case the design rules for bond wires (the spacing and the angle at which the bond wires leave the pads) become very important.</P>
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<IMG SRC="CH16-13.gif" ALIGN="BASELINE">
&nbsp;</P>
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FIGURE&nbsp;16.13&nbsp;<A NAME="11801">
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Bonding pads. (a)&nbsp;This chip uses both pad-limited and core-limited pads. (b)&nbsp;A hybrid corner pad. (c)&nbsp;A chip with stagger-bonded pads. (d)&nbsp;An area-bump bonded chip (or flip-chip). The chip is turned upside down and solder bumps connect the pads to the lead frame.</P>
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<P CLASS="Body">
<A NAME="pgfId=42346">
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<A HREF="CH16.1.htm#11801" CLASS="XRef">
Figure&nbsp;16.13</A>
(d) shows an <SPAN CLASS="Definition">
area-bump</SPAN>
<A NAME="marker=42345">
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 bonding arrangement (also known as <A NAME="marker=42347">
 </A>
flip-chip, <A NAME="marker=42359">
 </A>
solder-bump or <A NAME="marker=42358">
 </A>
C4, terms coined by IBM who developed this technology [<A NAME="Masleid91">
 </A>
Masleid, 1991]) used, for example, with <SPAN CLASS="Definition">
ball-grid array</SPAN>
<A NAME="marker=42348">
 </A>
 (<A NAME="marker=42349">
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<SPAN CLASS="Definition">
BGA</SPAN>
<A NAME="marker=83760">
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) packages. Even though the bonding pads are located in the center of the chip, the I/O circuits are still often located at the edges of the chip because of difficulties in power supply distribution and integrating I/O circuits together with logic in the center of the die. </P>
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<A NAME="pgfId=1493">
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In an MGA the pad spacing and I/O-cell spacing is fixed&#8212;each pad occupies a fixed <A NAME="marker=4466">
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<SPAN CLASS="Definition">
pad slot</SPAN>
 (or <SPAN CLASS="Definition">
pad site</SPAN>
<A NAME="marker=57672">
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). This means that the properties of the pad I/O are also fixed but, if we need to, we can parallel adjacent output cells to increase the drive. To increase flexibility further the I/O cells can use a separation, the <SPAN CLASS="Definition">
I/O-cell pitch</SPAN>
<A NAME="marker=58779">
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, that is smaller than the <SPAN CLASS="Definition">
pad pitch</SPAN>
<A NAME="marker=58780">
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. For example, three 4 mA driver cells can occupy two pad slots. Then we can use two 4 mA output cells in parallel to drive one pad, forming an 8 mA output pad as shown in <A HREF="CH16.1.htm#35024" CLASS="XRef">
Figure&nbsp;16.14</A>
. This arrangement also means the I/O pad cells can be changed without changing the base array. This is useful as bonding techniques improve and the pads can be moved closer together.</P>
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FIGURE&nbsp;16.14&nbsp;<A NAME="35024">
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Gate-array I/O pads. (a)&nbsp;Cell-based ASICs may contain pad cells of different sizes and widths. (b)&nbsp;A corner of a gate-array base. (c)&nbsp;A gate-array base with different I/O cell and pad pitches. </P>
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&nbsp;</P>
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FIGURE&nbsp;16.15&nbsp;<A NAME="26887">
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Power distribution. (a)&nbsp;Power distributed using m1 for VSS and m2 for VDD. This helps minimize the number of vias and layer crossings needed but causes problems in the routing channels. (b)&nbsp;In this floorplan m1 is run parallel to the longest side of all channels, the channel spine. This can make automatic routing easier but may increase the number of vias and layer crossings. (c)&nbsp;An expanded view of part of a channel (interconnect is shown as lines). If power runs on different layers along the spine of a channel, this forces signals to change layers. (d)&nbsp;A closeup of VDD and VSS buses as they cross. Changing layers requires a large number of via contacts to reduce resistance.</P>
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<A HREF="CH16.1.htm#26887" CLASS="XRef">
Figure&nbsp;16.15</A>
 shows two possible power distribution schemes. The long direction of a rectangular channel is the <A NAME="marker=1505">
 </A>
<SPAN CLASS="Definition">
channel spine</SPAN>
. Some automatic routers may require that metal lines parallel to a channel spine use a <A NAME="marker=1507">
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<SPAN CLASS="Definition">
preferred layer</SPAN>
 (either m1, m2, or m3). Alternatively we say that a particular metal layer runs in a <A NAME="marker=1509">
 </A>
<SPAN CLASS="Definition">
preferred direction</SPAN>
. Since we can have both horizontal and vertical channels, we may have the situation shown in <A HREF="CH16.1.htm#26887" CLASS="XRef">
Figure&nbsp;16.15</A>
, where we have to decide whether to use a preferred layer or the preferred direction for some channels. This may or may not be handled automatically by the routing software. </P>
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<DIV>
<H2 CLASS="Heading2">
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16.1.6&nbsp;<A NAME="25832">
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Clock Planning</H2>
<P CLASS="BodyAfterHead">
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<A HREF="CH16.1.htm#27899" CLASS="XRef">
Figure&nbsp;16.16</A>
(a) shows a <SPAN CLASS="Definition">
clock spine</SPAN>
<A NAME="marker=57701">
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 (not to be confused with a channel spine) routing scheme with all clock pins driven directly from the clock driver. MGAs and FPGAs often use this fish bone type of clock distribution scheme. <A HREF="CH16.1.htm#27899" CLASS="XRef">
Figure&nbsp;16.16</A>
(b) shows a clock spine for a cell-based ASIC. <A HREF="CH16.1.htm#27899" CLASS="XRef">
Figure&nbsp;16.16</A>
(c) shows the clock-driver cell, often part of a special clock-pad cell. <A HREF="CH16.1.htm#27899" CLASS="XRef">
Figure&nbsp;16.16</A>
(d) illustrates <SPAN CLASS="Definition">
clock skew</SPAN>
<A NAME="marker=57744">
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 and <SPAN CLASS="Definition">
clock latency</SPAN>
<A NAME="marker=57745">
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. Since all clocked elements are driven from one net with a clock spine, skew is caused by differing interconnect lengths and loads. If the clock-driver delay is much larger than the interconnect delays, a clock spine achieves minimum skew but with long latency.</P>
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FIGURE&nbsp;16.16&nbsp;<A NAME="27899">
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Clock distribution. (a)&nbsp;A clock spine for a gate array. (b)&nbsp;A clock spine for a cell-based ASIC (typical chips have thousands of clock nets). (c)&nbsp;A clock spine is usually driven from one or more clock-driver cells. Delay in the driver cell is a function of the number of stages and the ratio of output to input capacitance for each stage (taper). (d)&nbsp;Clock latency and clock skew. We would like to minimize both latency and skew.</P>
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Clock skew represents a fraction of the clock period that we cannot use for computation. A clock skew of 500 ps with a 200 MHz clock means that we waste 500 ps of every 5 ns clock cycle, or 10  percent of performance. Latency can cause a similar loss of performance at the system level when we need to resynchronize our output signals with a master system clock.</P>
<P CLASS="Body">
<A NAME="pgfId=21553">
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<A HREF="CH16.1.htm#27899" CLASS="XRef">
Figure&nbsp;16.16</A>
(c) illustrates the construction of a clock-driver cell. The delay through a chain of CMOS gates is minimized when the ratio between the input capacitance <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
1</SUB>
 and the output (load) capacitance <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
2</SUB>
 is about 3 (exactly e <SPAN CLASS="Symbol">
&#170; </SPAN>
2.7, an exponential ratio, if we neglect the effect of parasitics). This means that the fastest way to drive a large load is to use a chain of buffers with their input and output loads chosen to maintain this ratio, or <SPAN CLASS="Definition">
taper</SPAN>
<A NAME="marker=58856">
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 (we use this as a noun and a verb). This is not necessarily the smallest or lowest-power method, though.</P>
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Suppose we have an ASIC with the following specifications:</P>
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40,000 flip-flops</LI>
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Input capacitance of the clock input to each flip-flop is 0.025 pF</LI>
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Clock frequency is 200 MHz</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=52751">
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<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
 = 3.3 V</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=23460">
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Chip size is 20 mm on a side</LI>
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Clock spine consists of 200 lines across the chip</LI>
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<A NAME="pgfId=57362">
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Interconnect capacitance is 2 pFcm<SUP CLASS="Superscript">
&#8211;1</SUP>
</LI>
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In this case the clock-spine capacitance <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
 = 200 <SPAN CLASS="Symbol">
&#165;</SPAN>
 2 cm <SPAN CLASS="Symbol">
&#165;</SPAN>
 2 pFcm<SUP CLASS="Superscript">
&#8211;1</SUP>
 = 800 pF. If we drive the clock spine with a chain of buffers with taper equal to e <SPAN CLASS="Symbol">
&#170;</SPAN>
 2.7, and with a first-stage input capacitance of 0.025 pF (a reasonable value for a 0.5 <SPAN CLASS="Symbol">
m</SPAN>
m process), we will need  </P>
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&nbsp;</P>
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&nbsp;</P>
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800 <SPAN CLASS="Symbol">
&#165;</SPAN>
 10<SUP CLASS="Superscript">
&#8211;12</SUP>
</P>
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&nbsp;</P>
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&nbsp;</P>
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&nbsp;</P>
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