ch16.1.htm

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a). Then suppose we can slice each of these pieces into two. If we can continue in this fashion until all the blocks are separated, then we have a <A NAME="marker=85862">
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<SPAN CLASS="Definition">
slicing floorplan</SPAN>
 (<A HREF="CH16.1.htm#28692" CLASS="XRef">
Figure&nbsp;16.9</A>
b). <A HREF="CH16.1.htm#28692" CLASS="XRef">
Figure&nbsp;16.9</A>
(c) shows how the sequence we use to slice the chip defines a hierarchy of the blocks. Reversing the slicing order ensures that we route the stems of all the channel T-junctions first.</P>
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<A NAME="pgfId=85874">
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&nbsp;</P>
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<IMG SRC="CH16-10.gif">
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<P CLASS="TableFigureTitle">
<A NAME="pgfId=85877">
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FIGURE&nbsp;16.10&nbsp;<A NAME="20979">
 </A>
Cyclic constraints. (a)&nbsp;A nonslicing floorplan with a cyclic constraint that prevents channel routing. (b)&nbsp;In this case it is difficult to find a slicing floorplan without increasing the chip area. (c)&nbsp;This floorplan may be sliced (with initial cuts 1 or 2) and has no cyclic constraints, but it is inefficient in area use and will be very difficult to route. </P>
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<P CLASS="Body">
<A NAME="pgfId=85881">
 </A>
<A HREF="CH16.1.htm#20979" CLASS="XRef">
Figure&nbsp;16.10</A>
 shows a floorplan that is not a slicing structure. We cannot cut the chip all the way across with a knife without chopping a circuit block in two. This means we cannot route any of the channels in this floorplan without routing all of the other channels first. We say there is a <A NAME="marker=85882">
 </A>
<SPAN CLASS="Definition">
cyclic constraint</SPAN>
 in this floorplan. There are two solutions to this problem. One solution is to move the blocks until we obtain a slicing floorplan. The other solution is to allow the use of <EM CLASS="SansSerif">
L</EM>
-shaped, rather than rectangular, channels (or areas with fixed connectors on all sides&#8212;a <SPAN CLASS="Definition">
switch box</SPAN>
<A NAME="marker=85883">
 </A>
). We need an area-based router rather than a channel router to route <EM CLASS="SansSerif">
L</EM>
-shaped regions or switch boxes (see Section 17.2.6, &#8220;Area-Routing Algorithms&#8221;).</P>
<P CLASS="Body">
<A NAME="pgfId=1346">
 </A>
<A HREF="CH16.1.htm#36876" CLASS="XRef">
Figure&nbsp;16.11</A>
(a) displays the floorplan of the ASIC shown in <A HREF="CH16.1.htm#33899" CLASS="XRef">
Figure&nbsp;16.7</A>
. We can remove the cyclic constraint by moving the blocks again, but this increases the chip size. <A HREF="CH16.1.htm#36876" CLASS="XRef">
Figure&nbsp;16.11</A>
(b) shows an alternative solution. We <A NAME="marker=1338">
 </A>
<SPAN CLASS="Definition">
merge</SPAN>
 the flexible standard cell areas A and C. We can do this by <A NAME="marker=1341">
 </A>
<SPAN CLASS="Definition">
selective flattening</SPAN>
 of the netlist. Sometimes <A NAME="marker=1343">
 </A>
flattening can reduce the routing area because routing between blocks is usually less efficient than routing inside the row-based blocks. <A HREF="CH16.1.htm#36876" CLASS="XRef">
Figure&nbsp;16.11</A>
(b) shows the channel definition and <A NAME="marker=1345">
 </A>
<SPAN CLASS="Definition">
routing order</SPAN>
 for our chip.</P>
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<IMG SRC="CH16-11.gif" ALIGN="BASELINE">
&nbsp;</P>
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FIGURE&nbsp;16.11&nbsp;<A NAME="36876">
 </A>
Channel definition and ordering. (a)&nbsp;We can eliminate the cyclic constraint by merging the blocks A and C. (b)&nbsp;A slicing structure. </P>
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<DIV>
<H2 CLASS="Heading2">
<A NAME="pgfId=1355">
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16.1.5&nbsp;<A NAME="21222">
 </A>
I/O and Power Planning</H2>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=30068">
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Every chip communicates with the outside world. Signals flow onto and off the chip and we need to supply power. We need to consider the I/O and power constraints early in the floorplanning process. A silicon chip or <A NAME="marker=1359">
 </A>
<SPAN CLASS="Definition">
die</SPAN>
 (plural <A NAME="marker=18139">
 </A>
die, dies, or dice) is mounted on a <A NAME="marker=1362">
 </A>
<SPAN CLASS="Definition">
chip carrier</SPAN>
 inside a chip <A NAME="marker=1364">
 </A>
<SPAN CLASS="Definition">
package</SPAN>
. Connections are made by <A NAME="marker=1366">
 </A>
<SPAN CLASS="Definition">
bonding</SPAN>
 the chip <A NAME="marker=1368">
 </A>
<SPAN CLASS="Definition">
pads</SPAN>
 to fingers on a metal <A NAME="marker=1370">
 </A>
<SPAN CLASS="Definition">
lead frame</SPAN>
 that is part of the package. The metal lead-frame fingers connect to the <SPAN CLASS="Definition">
package pins</SPAN>
<A NAME="marker=57663">
 </A>
. A die consists of a logic <A NAME="marker=1377">
 </A>
<SPAN CLASS="Definition">
core</SPAN>
 inside a <A NAME="marker=1380">
 </A>
<SPAN CLASS="Definition">
pad ring</SPAN>
. <A HREF="CH16.1.htm#37173" CLASS="XRef">
Figure&nbsp;16.12</A>
(a) shows a <A NAME="marker=1382">
 </A>
<SPAN CLASS="Definition">
pad-limited die</SPAN>
 and <A HREF="CH16.1.htm#37173" CLASS="XRef">
Figure&nbsp;16.12</A>
(b) shows a <A NAME="marker=1384">
 </A>
<SPAN CLASS="Definition">
core-limited die</SPAN>
. On a pad-limited die we use tall, thin <A NAME="marker=1386">
 </A>
<SPAN CLASS="Definition">
pad-limited pads</SPAN>
, which maximize the number of pads we can fit around the outside of the chip. On a core-limited die we use short, wide <A NAME="marker=1388">
 </A>
<SPAN CLASS="Definition">
core-limited pads</SPAN>
. <A HREF="CH16.1.htm#37173" CLASS="XRef">
Figure&nbsp;16.12</A>
(c) shows how we can use both types of pad to change the aspect ratio of a die to be different from that of the core. </P>
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&nbsp;</P>
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<A NAME="pgfId=45617">
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FIGURE&nbsp;16.12&nbsp;<A NAME="37173">
 </A>
Pad-limited and core-limited die. (a)&nbsp;A pad-limited die. The number of pads determines the die size. (b)&nbsp;A core-limited die: The core logic determines the die size. (c)&nbsp;Using both pad-limited pads and core-limited pads for a square die.</P>
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<P CLASS="Body">
<A NAME="pgfId=1397">
 </A>
Special <A NAME="marker=1393">
 </A>
<SPAN CLASS="Definition">
power pads</SPAN>
 are used for the positive supply, or VDD, <SPAN CLASS="Definition">
power buses</SPAN>
<A NAME="marker=61847">
 </A>
 (or <A NAME="marker=61848">
 </A>
<SPAN CLASS="Definition">
power rails</SPAN>
) and the ground or negative supply, VSS or GND. Usually one set of VDD/VSS pads supplies one <A NAME="marker=1396">
 </A>
<SPAN CLASS="Definition">
power ring</SPAN>
 that runs around the pad ring and supplies power to the I/O pads only. Another set of VDD/VSS pads connects to a second power ring that supplies the logic core. We sometimes call the I/O power <SPAN CLASS="Definition">
dirty power</SPAN>
<A NAME="marker=5146">
 </A>
 since it has to supply large transient currents to the output transistors. We keep dirty power separate to avoid injecting noise into the internal-logic power (the <SPAN CLASS="Definition">
clean power</SPAN>
<A NAME="marker=5147">
 </A>
). I/O pads also contain special circuits to protect against <SPAN CLASS="Definition">
electrostatic discharge</SPAN>
<A NAME="marker=30093">
 </A>
 (<A NAME="marker=30092">
 </A>
<SPAN CLASS="Definition">
ESD</SPAN>
<A NAME="marker=85963">
 </A>
). These circuits can withstand very short high-voltage (several kilovolt) pulses that can be generated during human or machine handling.</P>
<P CLASS="Body">
<A NAME="pgfId=1408">
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Depending on the type of package and how the foundry attaches the silicon die to the <SPAN CLASS="Definition">
chip cavity</SPAN>
<A NAME="marker=23535">
 </A>
 in the chip carrier, there may be an electrical connection between the chip carrier and the die substrate. Usually the die is cemented in the chip cavity with a conductive epoxy, making an electrical connection between substrate and the package cavity in the chip carrier. If we make an electrical connection between the substrate and a chip pad, or to a package pin, it must be to VDD (<SPAN CLASS="EmphasisPrefix">
n</SPAN>
-type substrate) or VSS (<SPAN CLASS="EmphasisPrefix">
p</SPAN>
-type substrate). This <SPAN CLASS="Definition">
substrate connection</SPAN>
<A NAME="marker=9156">
 </A>
 (for the whole chip) employs a <A NAME="marker=1406">
 </A>
<SPAN CLASS="Definition">
down bond</SPAN>
 (or <A NAME="marker=5148">
 </A>
drop bond) to the carrier. We have several options:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=1412">
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We can dedicate one (or more) chip pad(s) to down bond to the chip carrier.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=1414">
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We can make a connection from a chip pad to the lead frame and down bond from the chip pad to the chip carrier.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=1416">
 </A>
We can make a connection from a chip pad to the lead frame and down bond from the lead frame.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=3361">
 </A>
We can down bond from the lead frame without using a chip pad.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=1420">
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We can leave the substrate and/or chip carrier unconnected.</LI>
</UL>
<P CLASS="Body">
<A NAME="pgfId=3376">
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Depending on the package design, the type and positioning of down bonds may be fixed. This means we need to fix the position of the chip pad for down bonding using a <A NAME="marker=1424">
 </A>
<SPAN CLASS="Definition">
pad seed</SPAN>
.</P>
<P CLASS="Body">
<A NAME="pgfId=27372">
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A <A NAME="marker=27371">
 </A>
<SPAN CLASS="Definition">
double bond</SPAN>
 connects two pads to one chip-carrier finger and one package pin. We can do this to save package pins or reduce the series inductance of bond wires (typically a few nanohenries) by parallel connection of the pads. A <A NAME="marker=27373">
 </A>
<SPAN CLASS="Definition">
multiple-signal pad</SPAN>
 or pad group is a set of pads. For example, an <A NAME="marker=27374">
 </A>
<SPAN CLASS="Definition">
oscillator pad</SPAN>
 usually comprises a set of two adjacent pads that we connect to an external crystal. The oscillator circuit and the two signal pads form a single logic cell. Another common example is a <A NAME="marker=27375">
 </A>
<SPAN CLASS="Definition">
clock pad</SPAN>
. Some foundries allow a special form of <A NAME="marker=27376">
 </A>
<SPAN CLASS="Definition">
corner pad</SPAN>
 (normal pads are <A NAME="marker=27377">
 </A>
<SPAN CLASS="Definition">
edge pads</SPAN>
) that squeezes two pads into the area at the corners of a chip using a special <A NAME="marker=27378">
 </A>
<SPAN CLASS="Definition">
two-pad corner cell</SPAN>
, to help meet <SPAN CLASS="Definition">
bond-wire angle design rules</SPAN>
<A NAME="marker=27379">
 </A>
 (see also <A HREF="CH16.1.htm#11801" CLASS="XRef">
Figure&nbsp;16.13</A>
b and c).</P>
<P CLASS="Body">
<A NAME="pgfId=1448">
 </A>
To reduce the series resistive and inductive impedance of power supply networks, it is normal to use <A NAME="marker=27395">
 </A>
multiple VDD and VSS pads. This is particularly important with the <A NAME="marker=1444">
 </A>
<SPAN CLASS="Definition">
simultaneously switching outputs</SPAN>
 (<A NAME="marker=1447">
 </A>
<SPAN CLASS="Definition">
SSOs</SPAN>
<A NAME="marker=83505">
 </A>
) that occur when driving buses off-chip [<A NAME="Wada90">
 </A>
Wada, Eino, and Anami, 1990]. The output pads can easily consume most of the power on a CMOS ASIC, because the load on a pad (usually tens of picofarads) is much larger than typical on-chip capacitive loads. Depending on the technology it may be necessary to provide dedicated VDD and VSS pads for every few SSOs. Design rules set how many SSOs can be used per VDD/VSS pad pair. These dedicated VDD/VSS pads must &#8220;follow&#8221; groups of output pads as they are seeded or planned on the floorplan. With some chip packages this can become difficult because design rules limit the location of package pins that may be used for supplies (due to the differing series inductance of each pin). </P>
<P CLASS="Body">
<A NAME="pgfId=1460">
 </A>
Using a <A NAME="marker=4441">
 </A>
<SPAN CLASS="Definition">
pad mapping</SPAN>
 we translate the <A NAME="marker=1452">
 </A>
<SPAN CLASS="Definition">
logical pad</SPAN>
 in a netlist to a <A NAME="marker=1455">
 </A>
<SPAN CLASS="Definition">
physical pad</SPAN>
 from a <A NAME="marker=1457">
 </A>
<SPAN CLASS="Definition">
pad library</SPAN>
. We might control pad seeding and mapping in the floorplanner. The handling of I/O pads can become quite complex; there are several nonobvious factors that must be considered when generating a pad ring:</P>
<UL>
<LI CLASS="BulletList">
<A NAME="pgfId=1464">