ch16.1.htm

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1.46 </P>
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11 k </P>
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	5.11 </P>
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0.84 </P>
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1.34 </P>
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2.25 </P>
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105 k </P>
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	12.50 </P>
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1.75 </P>
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2.70 </P>
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4.92  </P>
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<A HREF="CH16.1.htm#13660" CLASS="XRef">
Table&nbsp;16.1</A>
 shows the estimated metal interconnect lengths, as a function of die size and fanout, for a series of three-level metal gate arrays. In this case the interconnect capacitance is about 2 pFcm<SUP CLASS="Superscript">
&#8211;1</SUP>
, a typical figure. 						</P>
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<A HREF="CH16.1.htm#29800" CLASS="XRef">
Figure&nbsp;16.5</A>
 shows that, because we do not decrease chip size as we scale down feature size, the worst-case interconnect delay increases. One way to measure the worst-case delay uses an interconnect that completely crosses the chip, a <SPAN CLASS="Definition">
coast-to-coast interconnect</SPAN>
<A NAME="marker=29744">
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. In certain cases the worst-case delay of a 0.25 <SPAN CLASS="Symbol">
m</SPAN>
m process may be worse than a 0.35 <SPAN CLASS="Symbol">
m</SPAN>
m process, for example. </P>
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FIGURE&nbsp;16.5&nbsp;<A NAME="29800">
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Worst-case interconnect delay. As we scale circuits, but avoid scaling the chip size, the worst-case interconnect delay increases.</P>
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&nbsp;</P>
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16.1.3&nbsp;<A NAME="39431">
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Floorplanning Tools</H2>
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<A HREF="CH16.1.htm#36279" CLASS="XRef">
Figure&nbsp;16.6</A>
(a) shows an initial <A NAME="marker=79888">
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<SPAN CLASS="Definition">
random floorplan</SPAN>
 generated by a floorplanning tool. Two of the blocks, A and C in this example, are standard-cell areas (the chip shown in <A HREF="CH16.htm#35317" CLASS="XRef">
Figure&nbsp;16.1</A>
 is one large standard-cell area). These are <A NAME="marker=79904">
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<SPAN CLASS="Definition">
flexible blocks</SPAN>
 (or <SPAN CLASS="Definition">
variable blocks</SPAN>
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) because, although their total area is fixed, their shape (aspect ratio) and <A NAME="marker=79905">
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connector locations may be adjusted during the placement step. The dimensions and connector locations of the other <A NAME="marker=79907">
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<SPAN CLASS="Definition">
fixed blocks</SPAN>
 (perhaps RAM, ROM, compiled cells, or megacells) can only be modified when they are created. We may force logic cells to be in selected flexible blocks by <A NAME="marker=1229">
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<SPAN CLASS="Definition">
seeding</SPAN>
. We choose <A NAME="marker=1232">
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<SPAN CLASS="Definition">
seed cells</SPAN>
 by name. For example, <SPAN CLASS="BodyComputer">
ram_control*</SPAN>
 would select all logic cells whose names started with <SPAN CLASS="BodyComputer">
ram_control</SPAN>
 to be placed in one flexible block. The special symbol, usually '<SPAN CLASS="BodyComputer">
*</SPAN>
', is a <A NAME="marker=1234">
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<SPAN CLASS="Definition">
wildcard symbol</SPAN>
. Seeding may be hard or soft. A <A NAME="marker=1238">
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<SPAN CLASS="Definition">
hard seed</SPAN>
 is fixed and not allowed to move during the remaining floorplanning and placement steps. A <A NAME="marker=1240">
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<SPAN CLASS="Definition">
soft seed</SPAN>
 is an initial suggestion only and can be altered if necessary by the floorplanner. We may also use <A NAME="marker=5167">
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<SPAN CLASS="Definition">
seed connectors</SPAN>
 within flexible blocks&#8212;forcing certain nets to appear in a specified order, or location at the boundary of a flexible block.</P>
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FIGURE&nbsp;16.6&nbsp;<A NAME="36279">
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Floorplanning a cell-based ASIC. (a)&nbsp;Initial floorplan generated by the floorplanning tool. Two of the blocks are flexible (A and C) and contain rows of standard cells (unplaced). A pop-up window shows the status of block A. (b)&nbsp;An estimated placement for flexible blocks A and C. The connector positions are known and a rat&#8217;s nest display shows the heavy congestion below block B. (c)&nbsp;Moving blocks to improve the floorplan. (d)&nbsp;The updated display shows the reduced congestion after the changes.</P>
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The floorplanner can complete an estimated placement to determine the positions of connectors at the boundaries of the flexible blocks. <A HREF="CH16.1.htm#36279" CLASS="XRef">
Figure&nbsp;16.6</A>
(b) illustrates a <A NAME="marker=3100">
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<SPAN CLASS="Definition">
rat's nest</SPAN>
 display of the connections between blocks. Connections are shown as <SPAN CLASS="Definition">
bundles</SPAN>
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 between the centers of blocks or as <A NAME="marker=27590">
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flight lines</SPAN>
 between connectors. <A HREF="CH16.1.htm#36279" CLASS="XRef">
Figure&nbsp;16.6</A>
(c) and (d) show how we can move the blocks in a floorplanning tool to minimize routing <A NAME="marker=3103">
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<SPAN CLASS="Definition">
congestion</SPAN>
.</P>
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We need to control the <A NAME="marker=3164">
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<SPAN CLASS="Definition">
aspect ratio</SPAN>
 of our floorplan because we have to fit our chip into the <A NAME="marker=26191">
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<SPAN CLASS="Definition">
die cavity</SPAN>
 (a fixed-size hole, usually square) inside a package. <A HREF="CH16.1.htm#33899" CLASS="XRef">
Figure&nbsp;16.7</A>
(a)&#8211;(c) show how we can rearrange our chip to achieve a square aspect ratio. <A HREF="CH16.1.htm#33899" CLASS="XRef">
Figure&nbsp;16.7</A>
(c) also shows a <A NAME="marker=3175">
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<SPAN CLASS="Definition">
congestion map</SPAN>
, another form of <A NAME="marker=3176">
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<SPAN CLASS="Definition">
routability</SPAN>
 display. There is no standard measure of routability. Generally the <SPAN CLASS="Definition">
interconnect channels</SPAN>
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, (or <A NAME="marker=32543">
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wiring channels&#8212;I shall call them channels from now on) have a certain <A NAME="marker=3178">
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<SPAN CLASS="Definition">
channel capacity</SPAN>
; that is, they can handle only a fixed number of interconnects. One measure of congestion is the difference between the number of interconnects that we actually need, called the <SPAN CLASS="Definition">
channel density</SPAN>
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, and the channel capacity. Another measure, shown in <A HREF="CH16.1.htm#33899" CLASS="XRef">
Figure&nbsp;16.7</A>
(c), uses the ratio of channel density to the channel capacity. With practice, we can create a good initial placement by floorplanning and a pictorial display. This is one area where the human ability to recognize patterns and spatial relations is currently superior to a computer program&#8217;s ability. </P>
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FIGURE&nbsp;16.7&nbsp;<A NAME="33899">
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Congestion analysis. (a)&nbsp;The initial floorplan with a 2:1.5 die aspect ratio. (b)&nbsp;Altering the floorplan to give a 1:1 chip aspect ratio. (c)&nbsp;A trial floorplan with a congestion map. Blocks A and C have been placed so that we know the terminal positions in the channels. Shading indicates the ratio of channel density to the channel capacity. Dark areas show regions that cannot be routed because the channel congestion exceeds the estimated capacity. (d)&nbsp;Resizing flexible blocks A and C alleviates congestion.</P>
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FIGURE&nbsp;16.8&nbsp;<A NAME="37852">
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Routing a T-junction between two channels in two-level metal. The dots represent logic cell pins. (a)&nbsp;Routing channel A (the stem of the T) first allows us to adjust the width of channel B. (b)&nbsp;If we route channel B first (the top of the T), this fixes the width of channel A. We have to route the stem of a T-junction before we route the top.</P>
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16.1.4&nbsp;<A NAME="12827">
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Channel Definition</H2>
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During the floorplanning step we assign the areas between blocks that are to be used for interconnect. This process is known as <A NAME="marker=3183">
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<SPAN CLASS="Definition">
channel definition</SPAN>
 or <A NAME="marker=3184">
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<SPAN CLASS="Definition">
channel allocation</SPAN>
. <A HREF="CH16.1.htm#37852" CLASS="XRef">
Figure&nbsp;16.8</A>
 shows a T-shaped junction between two rectangular channels and illustrates why we must route the stem (vertical) of the T before the bar. The general problem of choosing the order of rectangular channels to route is <A NAME="marker=30048">
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<SPAN CLASS="Definition">
channel ordering</SPAN>
. </P>
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FIGURE&nbsp;16.9&nbsp;<A NAME="28692">
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Defining the channel routing order for a slicing floorplan using a slicing tree. (a)&nbsp;Make a cut all the way across the chip between circuit blocks. Continue slicing until each piece contains just one circuit block. Each cut divides a piece into two without cutting through a circuit block. (b)&nbsp;A sequence of cuts: 1, 2, 3, and 4 that successively slices the chip until only circuit blocks are left. (c)&nbsp;The slicing tree corresponding to the sequence of cuts gives the order in which to route the channels: 4, 3, 2, and finally 1.</P>
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<A HREF="CH16.1.htm#28692" CLASS="XRef">
Figure&nbsp;16.9</A>
 shows a floorplan of a chip containing several blocks. Suppose we cut along the block boundaries slicing the chip into two pieces (<A HREF="CH16.1.htm#28692" CLASS="XRef">
Figure&nbsp;16.9</A>