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<TITLE> 16.1 Floorplanning</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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16.1 <A NAME="40147">
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Floorplanning</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=29774">
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<A HREF="CH16.1.htm#31935" CLASS="XRef">
Figure 16.3</A>
shows that both interconnect delay and gate delay decrease as we scale down feature sizes—but at different rates. This is because interconnect capacitance tends to a limit of about 2 pFcm<SUP CLASS="Superscript">
–1</SUP>
for a minimum-width wire while gate delay continues to decrease (see Section 17.4, “Circuit Extraction and DRC”). Floorplanning allows us to predict this interconnect delay by estimating interconnect length. </P>
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FIGURE 16.3 <A NAME="31935">
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Interconnect and gate delays. As feature sizes decrease, both average interconnect delay and average gate delay decrease—but at different rates. This is because interconnect capacitance tends to a limit that is independent of scaling. Interconnect delay now dominates gate delay.</P>
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16.1.1 <A NAME="30823">
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Floorplanning Goals and Objectives</H2>
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The input to a floorplanning tool is a hierarchical netlist that describes the interconnection of the <SPAN CLASS="Definition">
blocks</SPAN>
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</A>
(RAM, ROM, ALU, cache controller, and so on); the logic cells (NAND, NOR, D flip-flop, and so on) within the blocks; and the logic cell <A NAME="marker=62507">
</A>
connectors (the terms <SPAN CLASS="Emphasis">
terminals</SPAN>
<A NAME="marker=62514">
</A>
, <SPAN CLASS="Emphasis">
pins</SPAN>
<A NAME="marker=32131">
</A>
, or <SPAN CLASS="Emphasis">
ports</SPAN>
<A NAME="marker=32133">
</A>
mean the same thing as <SPAN CLASS="Emphasis">
connectors</SPAN>
). The netlist is a logical description of the ASIC; the floorplan is a physical description of an ASIC. Floorplanning is thus a mapping between the logical description (the netlist) and the physical description (the floorplan). </P>
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The goals of floorplanning are to:</P>
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arrange the blocks on a chip,</LI>
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</A>
decide the location of the I/O pads, </LI>
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<A NAME="pgfId=9709">
</A>
decide the location and number of the power pads,</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=62519">
</A>
decide the type of power distribution, and</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=9710">
</A>
decide the location and type of clock distribution.</LI>
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The objectives of floorplanning are to minimize the chip area and minimize delay. Measuring area is straightforward, but measuring delay is more difficult and we shall explore this next.</P>
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16.1.2 <A NAME="37058">
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Measurement of Delay in Floorplanning</H2>
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Throughout the ASIC design process we need to predict the performance of the final layout. In floorplanning we wish to predict the interconnect delay before we complete any routing. Imagine trying to predict how long it takes to get from Russia to China without knowing where in Russia we are or where our destination is in China. Actually it is worse, because in floorplanning we may move Russia or China.</P>
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To predict delay we need to know the <SPAN CLASS="Definition">
parasitics</SPAN>
<A NAME="marker=29562">
</A>
associated with interconnect: the <SPAN CLASS="Definition">
interconnect capacitance</SPAN>
<A NAME="marker=29523">
</A>
(<A NAME="marker=25543">
</A>
<SPAN CLASS="Definition">
wiring capacitance</SPAN>
or <SPAN CLASS="Definition">
routing capacitance</SPAN>
<A NAME="marker=29532">
</A>
) as well as the interconnect resistance. At the floorplanning stage we know only the <SPAN CLASS="Definition">
fanout</SPAN>
<A NAME="marker=62600">
</A>
(<A NAME="marker=62599">
</A>
<SPAN CLASS="Definition">
FO</SPAN>
<A NAME="marker=67935">
</A>
) of a net (the number of gates driven by a net) and the size of the block that the net belongs to. We cannot predict the resistance of the various pieces of the interconnect path since we do not yet know the shape of the interconnect for a net. However, we can estimate the total length of the interconnect and thus estimate the total capacitance. We estimate interconnect length by collecting statistics from previously routed chips and analyzing the results. From these statistics we create tables that predict the interconnect capacitance as a function of net fanout and block size. A floorplanning tool can then use these <SPAN CLASS="Definition">
predicted-capacitance tables</SPAN>
<A NAME="marker=62568">
</A>
(also known as <SPAN CLASS="Definition">
interconnect-load tables</SPAN>
<A NAME="marker=83792">
</A>
or <SPAN CLASS="Definition">
wire-load tables</SPAN>
<A NAME="marker=62570">
</A>
). <A HREF="CH16.1.htm#19755" CLASS="XRef">
Figure 16.4</A>
shows how we derive and use wire-load tables and illustrates the following facts:</P>
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FIGURE 16.4 <A NAME="19755">
</A>
Predicted capacitance. (a) Interconnect lengths as a function of fanout (FO) and circuit-block size. (b) Wire-load table. There is only one capacitance value for each fanout (typically the average value). (c) The wire-load table predicts the capacitance and delay of a net (with a considerable error). Net A and net B both have a fanout of 1, both have the same predicted net delay, but net B in fact has a much greater delay than net A in the actual layout (of course we shall not know what the actual layout is until much later in the design process).</P>
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<A NAME="pgfId=17570">
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Typically between 60 and 70 percent of nets have a FO = 1.</LI>
<LI CLASS="BulletList">
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The distribution for a FO = 1 has a very long tail, stretching to interconnects that run from corner to corner of the chip.</LI>
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<A NAME="pgfId=82203">
</A>
The distribution for a FO = 1 often has two peaks, corresponding to a distribution for close neighbors in subgroups within a block, superimposed on a distribution corresponding to routing between subgroups.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=17584">
</A>
We often see a twin-peaked distribution at the chip level also, corresponding to separate distributions for <SPAN CLASS="Definition">
interblock routing</SPAN>
<A NAME="marker=57600">
</A>
(inside blocks) and <SPAN CLASS="Definition">
intrablock routing</SPAN>
<A NAME="marker=57601">
</A>
(between blocks).</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=17588">
</A>
The distributions for FO > 1 are more symmetrical and flatter than for FO = 1.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=17591">
</A>
The wire-load tables can only contain one number, for example the average net capacitance, for any one distribution. Many tools take a worst-case approach and use the 80- or 90-percentile point instead of the average. Thus a tool may use a predicted capacitance for which we know 90 percent of the nets will have less than the estimated capacitance.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=17592">
</A>
We need to repeat the statistical analysis for blocks with different sizes. For example, a net with a FO = 1 in a 25 k-gate block will have a different (larger) average length than if the net were in a 5 k-gate block.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=17609">
</A>
The statistics depend on the shape (aspect ratio) of the block (usually the statistics are only calculated for square blocks).</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=17610">
</A>
The statistics will also depend on the type of netlist. For example, the distributions will be different for a netlist generated by setting a constraint for minimum logic delay during synthesis—which tends to generate large numbers of two-input NAND gates—than for netlists generated using minimum-area constraints.</LI>
</UL>
<P CLASS="Body">
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There are no standards for the wire-load tables themselves, but there are some standards for their use and for presenting the extracted loads (see <A HREF="CH16.4.htm#24725" CLASS="XRef">
Section 16.4</A>
). Wire-load tables often present loads in terms of a <SPAN CLASS="Definition">
standard load</SPAN>
<A NAME="marker=26624">
</A>
that is usually the input capacitance of a two-input NAND gate with a 1X (default) drive strength. </P>
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TABLE 16.1 <A NAME="13660">
</A>
A wire-load table showing average interconnect lengths (mm).<A HREF="#pgfId=94797" CLASS="footnote">
1</A>
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</SPAN>
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<P CLASS="Table">
<A NAME="pgfId=94813">
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<SPAN CLASS="TableHeads">
Fanout</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=94815">
</A>
<SPAN CLASS="TableHeads">
</SPAN>
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<A NAME="pgfId=94817">
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Array (available gates)</SPAN>
</P>
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<P CLASS="Table">
<A NAME="pgfId=94819">
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<SPAN CLASS="TableHeads">
Chip size (mm)</SPAN>
</P>
</TD>
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<P CLASS="Table">
<A NAME="pgfId=94821">
</A>
<SPAN CLASS="TableHeads">
1</SPAN>
</P>
</TD>
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<P CLASS="Table">
<A NAME="pgfId=94823">
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<SPAN CLASS="TableHeads">
2</SPAN>
</P>
</TD>
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<P CLASS="Table">
<A NAME="pgfId=94825">
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<SPAN CLASS="TableHeads">
4</SPAN>
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3 k </P>
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3.45 </P>
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0.56 </P>
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<A NAME="pgfId=94833">
</A>
0.85 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
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