ch16.htm
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<TITLE> FLOORPLANNING AND PLACEMENT</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
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FLOORPLANNING <BR>
AND <BR>
PLACEMENT</H1>
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The input to the floorplanning step is the output of system partitioning and design entry—a netlist. Floorplanning precedes placement, but we shall cover them together. The output of the placement step is a set of directions for the routing tools.</P>
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At the start of floorplanning we have a netlist describing circuit blocks, the logic cells within the blocks, and their connections. For example, <A HREF="CH16.htm#35317" CLASS="XRef">
Figure 16.1</A>
shows the Viterbi decoder example as a collection of standard cells with no room set aside yet for routing. We can think of the standard cells as a hod of bricks to be made into a wall. What we have to do now is set aside spaces (we call these spaces the <SPAN CLASS="Definition">
channels</SPAN>
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) for interconnect, the mortar, and arrange the cells. <A HREF="CH16.htm#38364" CLASS="XRef">
Figure 16.2</A>
shows a finished wall—after floorplanning and placement steps are complete. We still have not completed any routing at this point—that comes later—all we have done is placed the logic cells in a fashion that we hope will minimize the total interconnect length, for example. </P>
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FIGURE 16.1 <A NAME="35317">
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The starting point for the floorplanning and placement steps for the Viterbi decoder (containing only standard cells). This is the initial display of the floorplanning and placement tool. The small boxes that look like bricks are the outlines of the standard cells. The largest standard cells, at the bottom of the display (labeled dfctnb) are 188 D flip-flops. The '+' symbols represent the drawing origins of the standard cells—for the D flip-flops they are shifted to the left and below the logic cell bottom left-hand corner. The large box surrounding all the logic cells represents the estimated chip size. (This is a screen shot from Cadence Cell Ensemble.)</P>
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FIGURE 16.2 <A NAME="38364">
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The Viterbi Decoder (from <A HREF="CH16.htm#35317" CLASS="XRef">
Figure 16.1</A>
) after floorplanning and placement. There are 18 rows of standard cells separated by 17 horizontal channels (labeled 2–18). The channels are routed as numbered. In this example, the I/O pads are omitted to show the cell placement more clearly. Figure 17.1 shows the same placement without the channel labels. (A screen shot from Cadence Cell Ensemble.)</P>
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<H1 CLASS="Heading1TOC">
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16.1 Floorplanning</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH16.2.htm#pgfId=1525" CLASS="Hypertext">
16.2 Placement</A>
</H1>
<H1 CLASS="Heading1TOC">
<A HREF="CH16.3.htm#pgfId=27076" CLASS="Hypertext">
16.3 Physical Design Flow</A>
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<A HREF="CH16.4.htm#pgfId=27094" CLASS="Hypertext">
16.4 Information Formats</A>
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16.5 Summary</A>
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16.6 Problems</A>
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16.7 Bibliography</A>
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16.8 References</A>
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