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16.3 Physical <A NAME="21496">
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Design Flow</H1>
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Historically placement was included with routing as a single tool (the term <A NAME="marker=86393">
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P&R<A NAME="marker=86394">
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is often used for place and route). Because interconnect delay now dominates gate delay, the trend is to include placement within a floorplanning tool and use a separate router. <A HREF="CH16.3.htm#17157" CLASS="XRef">
Figure 16.31</A>
shows a <A NAME="marker=29854">
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design flow using synthesis and a floorplanning tool that includes placement. This flow consists of the following steps:</P>
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Design entry. </SPAN>
The input is a logical description with no physical information.</LI>
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Synthesis. </SPAN>
The initial synthesis contains little or no information on any interconnect loading. The output of the synthesis tool (typically an EDIF netlist) is the input to the floorplanner.</LI>
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Initial floorplan. </SPAN>
From the initial floorplan interblock capacitances are input to the synthesis tool as load constraints and intrablock capacitances are input as wire-load tables.</LI>
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Synthesis with load constraints.</SPAN>
At this point the synthesis tool is able to resynthesize the logic based on estimates of the interconnect capacitance each gate is driving. The synthesis tool produces a forward annotation file to constrain path delays in the placement step.</LI>
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FIGURE 16.31 <A NAME="17157">
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Timing-driven floorplanning and placement design flow. Compare with Figure 15.1 on p. 806.</P>
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Timing-driven placement.</SPAN>
After placement using constraints from the synthesis tool, the location of every logic cell on the chip is fixed and accurate estimates of interconnect delay can be passed back to the synthesis tool.</LI>
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Synthesis </SPAN>
with <SPAN CLASS="Definition">
in-place optimization</SPAN>
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(<SPAN CLASS="Definition">
IPO</SPAN>
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). The synthesis tool changes the drive strength of gates based on the accurate interconnect delay estimates from the floorplanner without altering the netlist structure.</LI>
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Detailed placement.</SPAN>
The placement information is ready to be input to the routing step.</LI>
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In <A HREF="CH16.3.htm#17157" CLASS="XRef">
Figure 16.31</A>
we iterate between floorplanning and synthesis, continuously improving our estimate for the interconnect delay as we do so. </P>
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