ch03.7.htm
来自「介绍asci设计的一本书」· HTM 代码 · 共 198 行
HTM
198 行
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML EXPERIMENTAL 970324//EN">
<HTML>
<HEAD>
<META NAME="GENERATOR" CONTENT="Adobe FrameMaker 5.5/HTML Export Filter">
<TITLE> 3.7 Standard-Cell Design</TITLE></HEAD><!--#include file="top.html"--><!--#include file="header.html"-->
<DIV>
<P>[ <A HREF="CH03.htm">Chapter start</A> ] [ <A HREF="CH03.6.htm">Previous page</A> ] [ <A HREF="CH03.8.htm">Next page</A> ]</P><!--#include file="AmazonAsic.html"--><HR></DIV>
<H1 CLASS="Heading1">
<A NAME="pgfId=159481">
</A>
3.7 <A NAME="39064">
</A>
Standard-Cell Design</H1>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=132049">
</A>
Figure <A HREF="#15737" CLASS="XRef">
3.19</A>
shows the components of the standard cell from Figure 1.3. Each standard cell in a library is rectangular with the same height but different widths. The <SPAN CLASS="Definition">
bounding box</SPAN>
<A NAME="marker=73691">
</A>
(<SPAN CLASS="Definition">
BB</SPAN>
<A NAME="marker=73692">
</A>
<A NAME="marker=73693">
</A>
) of a logic cell is the smallest rectangle that encloses all of the geometry of the cell. The cell BB is normally determined by the well layers. Cell connectors or terminals (the <SPAN CLASS="Definition">
logical connectors</SPAN>
<A NAME="marker=129920">
</A>
) must be placed on the cell <SPAN CLASS="Definition">
abutment box</SPAN>
<A NAME="marker=73694">
</A>
(<SPAN CLASS="Definition">
AB</SPAN>
<A NAME="marker=73695">
</A>
<A NAME="marker=73696">
</A>
). The <SPAN CLASS="Definition">
physical connector</SPAN>
<A NAME="marker=129921">
</A>
(the piece of metal to which we connect wires) must normally <A NAME="marker=99259">
</A>
overlap the abutment box slightly, usually by at least 1<SPAN CLASS="Symbol">
l</SPAN>
, to assure connection without leaving a tiny space between the ends of two wires. The standard cells are constructed so they can all be placed next to each other horizontally with the cell ABs touching (we <A NAME="marker=73697">
</A>
<SPAN CLASS="Definition">
abut</SPAN>
two cells).</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=132058">
</A>
(a)</P>
<P CLASS="TableFigure">
<A NAME="pgfId=187359">
</A>
</P>
<DIV>
<IMG SRC="CH03-33.gif">
</DIV>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=132090">
</A>
(b)</P>
<P CLASS="TableFigure">
<A NAME="pgfId=187358">
</A>
</P>
<DIV>
<IMG SRC="CH03-34.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=132233">
</A>
(c)</P>
<DIV>
<IMG SRC="CH03-35.gif">
</DIV>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=132235">
</A>
(d)</P>
<DIV>
<IMG SRC="CH03-36.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=132061">
</A>
FIGURE 3.19 <A NAME="15737">
</A>
(a) The standard cell shown in Figure 1.3. (b) Diffusion, poly, and contact layers. (c) m1 and contact layers. (d) The equivalent schematic.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=39272">
</A>
A standard cell (a D flip-flop with clear) is shown in Figure <A HREF="#10967" CLASS="XRef">
3.20</A>
and illustrates the following features of standard-cell layout: </P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=39295">
</A>
Layout using 45° angles. This can save 10%–20% in area compared to a cell that uses only Manhattan or 90° geometry. Some ASIC vendors do not allow transistors with 45° angles; others do not allow 45° angles at all.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=39296">
</A>
Connectors are at the top and bottom of the cell on m2 on a routing grid equal to the vertical (m2) track spacing. This is a double-entry cell intended for a two-level metal process. A standard cell designed for a three-level metal process has connectors in the center of the cell.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=39306">
</A>
Transistor sizes vary to optimize the area and performance but maintain a fixed ratio to balance rise times and fall times.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=39322">
</A>
The cell height is 64<SPAN CLASS="Symbol">
l</SPAN>
(all cells in the library are the same height) with a horizontal (m1) track spacing of 8<SPAN CLASS="Symbol">
l</SPAN>
. This is close to the minimum height that can accommodate the most complex cells in a library.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=39323">
</A>
The power rails are placed at the top and bottom, maintaining a certain width inside the cell and abut with the power rails in adjacent cells.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=39325">
</A>
The well contacts (substrate connections) are placed inside the cell at regular intervals. Additional well contacts may be placed in spacers between cells.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=94877">
</A>
In this case both wells are drawn. Some libraries minimize the well or moat area to reduce leakage and parasitic capacitance.</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=39326">
</A>
Most commercial standard cells use m1 for the power rails, m1 for internal connections, and avoid using m2 where possible except for cell connectors.</LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=140903">
</A>
<IMG SRC="CH03-37.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=140906">
</A>
FIGURE 3.20 <A NAME="10967">
</A>
A D flip-flop standard cell. The wide power buses and transistors show this is a performance-optimized cell. This double-entry cell is intended for a two-level metal process and channel routing. The five connectors run vertically through the cell on m2 (the extra short vertical metal line is an internal crossover). </P>
</TD>
</TR>
</TABLE>
</UL>
<P CLASS="Body">
<A NAME="pgfId=158937">
</A>
When a library developer creates a gate-array, standard-cell, or datapath library, there is a trade-off between using wide, high-drive transistors that result in large cells with high-speed performance and using smaller transistors that result in smaller cells that consume less power. A <A NAME="marker=158938">
</A>
<SPAN CLASS="Definition">
performance-optimized library</SPAN>
with large cells might be used for ASICs in a high-performance workstation, for example. An <A NAME="marker=158939">
</A>
<SPAN CLASS="Definition">
area-optimized library</SPAN>
might be used in an ASIC for a battery-powered portable computer. </P>
<HR><P>[ <A HREF="CH03.htm">Chapter start</A> ] [ <A HREF="CH03.6.htm">Previous page</A> ] [ <A HREF="CH03.8.htm">Next page</A> ]</P></BODY>
<!--#include file="Copyright.html"--><!--#include file="footer.html"-->
⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?