ch03.3.htm

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&nbsp;</P>
</TD>
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<P CLASS="BodyAfterHead">
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 </A>
The time constant <SPAN CLASS="Definition">
tau</SPAN>
<A NAME="marker=140984">
 </A>
,  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=222204">
 </A>
<SPAN CLASS="Symbol">
t</SPAN>
 = <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="Subscript">
inv </SUB>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
inv</SUB>
 ,</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=222206">
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<A NAME="21151">
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(3.16)</P>
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</TABLE>
<P CLASS="BodyAfterHead">
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is a basic property of any CMOS technology. We shall measure delays in terms of <SPAN CLASS="Symbol">
t</SPAN>
. </P>
<P CLASS="Body">
<A NAME="pgfId=87921">
 </A>
The delay equation for a 1X (minimum-size) inverter in the C5 library is  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=222268">
 </A>
<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PDf </SUB>
&nbsp;= <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
(<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
out </SUB>
+ <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
) ln (1/0.35) <SPAN CLASS="Symbol">
&#170; </SPAN>
<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
(<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
out</SUB>
 + <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
) .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=222270">
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<A NAME="32931">
 </A>
(3.17)</P>
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</TR>
</TABLE>
<P CLASS="BodyAfterHead">
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Thus <SPAN CLASS="EquationVariables">
tq</SPAN>
<SUB CLASS="Subscript">
inv</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.1<SPAN CLASS="Symbol">
 </SPAN>
ns and <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="Subscript">
inv</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
1.60<SPAN CLASS="Symbol">
 </SPAN>
k<SPAN CLASS="Symbol">
W</SPAN>
 . The input capacitance of the 1X inverter (the standard load for this library) is specified in the data book as <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
inv</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.036<SPAN CLASS="Symbol">
 </SPAN>
pF; thus <SPAN CLASS="Symbol">
t </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
(0.036<SPAN CLASS="Symbol">
 </SPAN>
pF)(1.60<SPAN CLASS="Symbol">
 </SPAN>
k<SPAN CLASS="Symbol">
W</SPAN>
)<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.06<SPAN CLASS="Symbol">
 </SPAN>
ns for the C5 technology.</P>
<P CLASS="Body">
<A NAME="pgfId=160070">
 </A>
The use of logical effort consists of rearranging and understanding the meaning of the various terms in Eq.&nbsp;<A HREF="#28075" CLASS="XRef">
3.15</A>
. The delay equation is the sum of three terms,  </P>
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<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
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 </A>
<SPAN CLASS="EquationVariables">
d</SPAN>
 = <SPAN CLASS="EquationVariables">
f</SPAN>
 + <SPAN CLASS="EquationVariables">
p</SPAN>
 + <SPAN CLASS="EquationVariables">
q </SPAN>
.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=222279">
 </A>
(3.18)</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
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We give these terms special names as follows:  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=222432">
 </A>
delay = effort&nbsp;delay&nbsp;+&nbsp;parasitic&nbsp;delay&nbsp;+&nbsp;nonideal&nbsp;delay .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
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 </A>
(3.19)</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
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The <SPAN CLASS="Definition">
effort delay</SPAN>
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 </A>
 <SPAN CLASS="EquationVariables">
f</SPAN>
 we write as a product of logical effort, <SPAN CLASS="EquationVariables">
g</SPAN>
, and electrical effort, <SPAN CLASS="EquationVariables">
h:</SPAN>
  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=222456">
 </A>
<SPAN CLASS="EquationVariables">
f</SPAN>
<SUB CLASS="SubscriptVariable">
 </SUB>
= <SPAN CLASS="EquationVariables">
gh</SPAN>
 .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=222458">
 </A>
(3.20)</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=87944">
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So we can further partition delay into the following terms:  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=222469">
 </A>
delay = logical effort <SPAN CLASS="Symbol">
&#165;</SPAN>
 electrical effort + parasitic delay + nonideal delay .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=222471">
 </A>
(3.21)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
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The <SPAN CLASS="Definition">
logical effort</SPAN>
<A NAME="marker=87946">
 </A>
 <SPAN CLASS="EquationVariables">
g</SPAN>
 is a function of the type of logic cell,  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
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 </A>
<SPAN CLASS="EquationVariables">
g</SPAN>
<SUB CLASS="SubscriptVariable">
 </SUB>
= <SPAN CLASS="EquationVariables">
RC/</SPAN>
<SPAN CLASS="Symbol">
t</SPAN>
 .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=222495">
 </A>
(3.22)</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
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What size of logic cell do the <SPAN CLASS="EquationVariables">
R</SPAN>
 and <SPAN CLASS="EquationVariables">
C</SPAN>
 refer to? It does not matter because the <SPAN CLASS="EquationVariables">
R</SPAN>
 and <SPAN CLASS="EquationVariables">
C</SPAN>
 will change as we scale a logic cell, but the <SPAN CLASS="EquationVariables">
RC</SPAN>
 product stays the same&#8212;the logical effort is independent of the size of a logic cell. We can find the logical effort by scaling down the logic cell so that it has the same drive capability as the 1X minimum-size inverter. Then the logical effort, <SPAN CLASS="EquationVariables">
g</SPAN>
, is the ratio of the input capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
in</SUB>
, of the 1X version of the logic cell to <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
inv</SUB>
 (see Figure&nbsp;<A HREF="#17037" CLASS="XRef">
3.8</A>
).  </P>
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<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
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&nbsp;</P>
<DIV>
<IMG SRC="CH03-18.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
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FIGURE&nbsp;3.8&nbsp;<A NAME="17037">
 </A>
<A NAME="12429">
 </A>
Logical effort. (a)&nbsp;The input capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
inv</SUB>
, looking into the input of a minimum-size inverter in terms of the gate capacitance of a minimum-size device. (b)&nbsp;Sizing a logic cell to have the same drive strength as a minimum-size inverter (assuming a logic ratio of 2). The input capacitance looking into one of the logic-cell terminals is then <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
in</SUB>
. (c)&nbsp;The logical effort of a cell is <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
in</SUB>
/ <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
inv</SUB>
. For a two-input NAND cell, the logical effort, <SPAN CLASS="EquationVariables">
g</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
4/3.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=87954">
 </A>
The <SPAN CLASS="Definition">
electrical effort</SPAN>
<A NAME="marker=87953">
 </A>
 <SPAN CLASS="EquationVariables">
h</SPAN>
 depends only on the load capacitance <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
out</SUB>
 connected to the output of the logic cell and the input capacitance of the logic cell, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
in</SUB>
; thus  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=222577">
 </A>
<SPAN CLASS="EquationVariables">
h </SPAN>
= <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
out</SUB>
 /<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
in</SUB>
 .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=222579">
 </A>
(3.23)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
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The <SPAN CLASS="Definition">
parasitic delay</SPAN>
<A NAME="marker=87959">
 </A>
 <SPAN CLASS="EquationVariables">
p</SPAN>
 depends on the intrinsic parasitic capacitance <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
 of the logic cell, so that  </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=222593">
 </A>
<SPAN CLASS="EquationVariables">
p</SPAN>
<SUB CLASS="SubscriptVariable">
 </SUB>
= <SPAN CLASS="EquationVariables">
RC</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
/<SPAN CLASS="Symbol">
t</SPAN>
 .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=222595">
 </A>
(3.24)</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
<A NAME="pgfId=109055">
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Table&nbsp;<A HREF="#26377" CLASS="XRef">
3.2</A>
 shows the logical efforts for single-stage logic cells. Suppose the minimum-size inverter has an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor with W/L<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
1 and a <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor with W/L<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
2 (logic ratio, <SPAN CLASS="EquationVariables">
r</SPAN>
, of 2). Then each two-input NAND logic cell input is connected to an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor with W/L<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
2 and a <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor with W/L<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
2. The input capacitance of the two-input NAND logic cell divided by that of the inverter is thus 4/3. This is the logical effort of a two-input NAND when <SPAN CLASS="EquationVariables">
r</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
2. Logical effort depends on the ratio of the logic. For an <SPAN CLASS="EquationVariables">
n</SPAN>
-input NAND cell with ratio <SPAN CLASS="EquationVariables">
r</SPAN>
, the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistors are W/L<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
<SPAN CLASS="EquationVariables">
r</SPAN>
/1, and the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistors are W/L<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
<SPAN CLASS="EquationVariables">
n</SPAN>
/1. For a NOR cell the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistors are 1/1 and the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistors are <SPAN CLASS="EquationVariables">
nr</SPAN>
/1.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=153762">
 </A>
TABLE&nbsp;3.2&nbsp;<A NAME="26377">
 </A>
Cell effort, parasitic delay, and nonideal delay (in units of <SPAN CLASS="Symbol">
t</SPAN>
) for single-stage CMOS cells.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=153772">
 </A>
<SPAN CLASS="TableHeads">
Cell</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
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Cell effort</P>
<P CLASS="TableFirst">
<A NAME="pgfId=153775">
 </A>
(logic ratio<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
2)</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=153777">
 </A>
Cell effort</P>
<P CLASS="TableFirst">
<A NAME="pgfId=153778">
 </A>
(logic ratio<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>