ch03.5.htm
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3.5 <A NAME="40096">
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Library Architecture</H1>
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Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(a) shows cell use data from over 150 CMOS gate array designs. These results are remarkably similar to that from other ASIC designs using different libraries and different technologies and show that typically 80<SPAN CLASS="Symbol">
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percent of an ASIC uses less than 20<SPAN CLASS="Symbol">
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percent of the cell library. </P>
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(a)</SPAN>
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(b</SPAN>
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(c)</SPAN>
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(d)</SPAN>
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FIGURE 3.13 <A NAME="28051">
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Cell library statistics.</P>
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(e</SPAN>
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We can use the data in Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(a) to derive some useful conclusions about the number and types of cells to be included in a library. Before we do this, a few words of caution are in order. First, the data shown in Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(a) tells us about cells that are included a library. This data cannot tell us anything about cells that are not (and perhaps should be) included in a library. Second, the type of design entry we use—and the type of ASIC we are designing—can dramatically affect the profile of the use of different cell types. For example, if we use a high-level design language, together with logic synthesis, to enter an ASIC design, this will favor the use of the complex combinational cells (cells of the AOI family that are particularly area efficient in CMOS, but are difficult to work with when we design by hand). </P>
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Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(a) tells us which cells we use most often, but does not take into account the cell area. What we really want to know are which cells are most important in determining the area of an ASIC. Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(b) shows the area of the cells—normalized to the area of a minimum-size inverter. If we take the data in Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(a) and multiply by the cell areas, we can derive a new measure of the contribution of each cell in a library (Figure 3.13c). This new measure, <SPAN CLASS="Definition">
cell importance</SPAN>
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, is a measure of how much area each cell in a library contributes to a typical ASIC. For example, we can see from Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(c) that a D flip-flop (with a cell importance of 3.5) contributes 3.5 times as much area on a typical ASIC than does an inverter (with a cell importance of 1).</P>
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Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(c) shows cell importance ordered by the cell frequency of use and normalized to an inverter. We can rearrange this data in terms of cell importance, as shown in Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(d), and normalized so that now the most important cell, a D flip-flop, has a cell importance of 1. Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(e) includes the cell use data on the same scale as the cell importance data. Both show roughly the same shape, reflecting that both measures obey an 80–20 rule. Roughly 20<SPAN CLASS="Symbol">
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percent of the cells in a library correspond to 80<SPAN CLASS="Symbol">
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percent of the ASIC area and 80<SPAN CLASS="Symbol">
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percent of the cells we use (but not the same 20<SPAN CLASS="Symbol">
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percent—that is why cell importance is useful).</P>
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Figure <A HREF="#28051" CLASS="XRef">
3.13</A>
(e) shows us that the most important cells, measured by their contribution to the area of an ASIC, are not necessarily the cells that we use most often. If we wish to build or buy a dense library, we must concentrate on the area of those cells that have the highest cell importance—not the most common cells.</P>
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