ch03.a.htm

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<SPAN CLASS="TableHeads">
Actual implementation</SPAN>
<A HREF="#pgfId=212703" CLASS="footnote">
1</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=212706">
 </A>
<SPAN CLASS="TableHeads">
Alternative implementation(s) </SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=212708">
 </A>
XOR2D1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212710">
 </A>
AOI21[a1, a2, NOR(a1,a2)]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212712">
 </A>
not[mux(a1, not(a1), a2)]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=212714">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212716">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212718">
 </A>
aoi22(a1, a2, not(a1), not(a2))</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=212720">
 </A>
XOR2D2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212722">
 </A>
NOT[MUX(a1, not(a1), a2)]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212724">
 </A>
aoi21[a1, a2, nor(a1, a2)]</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=212726">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212728">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212730">
 </A>
aoi22(a1, a2, not(a1), not(a2))</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=212732">
 </A>
XOR3D1</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212734">
 </A>
NOT[MUX[a1, not(a1), not(mux(a3, not(a3), a2))]]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212736">
 </A>
?</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=212738">
 </A>
XOR3D2</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212740">
 </A>
NOT[MUX[a1, not(a1), not(mux(a3, not(a3), a2))]]</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=212742">
 </A>
?</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=123548">
 </A>
3.23&nbsp;(Library density, 10 min.) Derive an upper limit on cell density as follows: Assume a chip consists only of two-input NAND cells with no routing channels between rows (often achievable in a 3LM process with over-the-cell routing).</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=123456">
 </A>
a.&nbsp;Explain how many vertical tracks you need to connect to a two-input NAND cell, assuming each connection requires a separate track.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=123457">
 </A>
b.&nbsp;If the NAND cell is 64<SPAN CLASS="Symbol">
 l</SPAN>
 high with a vertical track width of 8<SPAN CLASS="Symbol">
 l</SPAN>
, calculate the NAND cell area, carefully explaining any assumptions. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=123458">
 </A>
c.&nbsp;Calculate the cell density (in gate/mil<SUP CLASS="Superscript">
2</SUP>
) for a 0.35<SPAN CLASS="Symbol">
 m</SPAN>
m process, <SPAN CLASS="Symbol">
l </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.175<SPAN CLASS="Symbol">
 m</SPAN>
m.</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=137422">
 </A>
<SPAN CLASS="Emphasis">
Answer:</SPAN>
 3 tracks, 47 <SPAN CLASS="Symbol">
m</SPAN>
m<SUP CLASS="Superscript">
2</SUP>
, 13.7 gates/mil<SUP CLASS="Superscript">
2</SUP>
 or 21 <SPAN CLASS="Symbol">
&#165;</SPAN>
 103 gates/mm<SUP CLASS="Superscript">
2</SUP>
.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=136014">
 </A>
3.24&nbsp;(Gate-array density, 20 min.) The LSI Logic 10k and 100k gate arrays use a four-transistor base cell, equivalent to 1 gate, that is 12 tracks high and 3 tracks wide.</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=123473">
 </A>
a.&nbsp;If a metal track is 8l, where l =<SPAN CLASS="Symbol">
 </SPAN>
0.75<SPAN CLASS="Symbol">
 m</SPAN>
m for a 1.5<SPAN CLASS="Symbol">
 m</SPAN>
m technology, calculate the area of the LSI Logic base cell <SPAN CLASS="EquationVariables">
A</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
 in mil<SUP CLASS="Superscript">
2</SUP>
.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=123474">
 </A>
b.&nbsp;If we could use every base cell in the gate array, the cell density would be <SPAN CLASS="EquationVariables">
D</SPAN>
<SUB CLASS="SubscriptVariable">
G</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
1/<SPAN CLASS="EquationVariables">
A</SPAN>
<SUB CLASS="SubscriptVariable">
L</SUB>
. Assume that, because of routing area and inefficiency of the gate array, we can use only 50 percent of the base cells for logic. What is <SPAN CLASS="EquationVariables">
D</SPAN>
<SUB CLASS="SubscriptVariable">
G</SUB>
 for the LSI Logic 1.5<SPAN CLASS="Symbol">
 m</SPAN>
m array?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=212020">
 </A>
c.&nbsp;Chip cell density <SPAN CLASS="EquationVariables">
D</SPAN>
<SUB CLASS="SubscriptVariable">
G</SUB>
 is about 1.0 gate/mil<SUP CLASS="Superscript">
2</SUP>
 for a 1 <SPAN CLASS="Symbol">
m</SPAN>
m technology (a two-input NAND cell occupies an area 25<SPAN CLASS="Symbol">
 m</SPAN>
m on a side in a technology whose transistors are 1 <SPAN CLASS="Symbol">
m</SPAN>
m long). This can change by a factor of 2 or more for a gate-array/standard-cell ASIC or high-density/high-performance library. Assume that cell density <SPAN CLASS="EquationVariables">
D</SPAN>
<SUB CLASS="SubscriptVariable">
G</SUB>
 scales ideally with technology. If the minimum feature size of a technology is 2l, then <SPAN CLASS="EquationVariables">
D</SPAN>
<SUB CLASS="SubscriptVariable">
G</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
&#8733;<SPAN CLASS="Symbol">
 </SPAN>
1/<SPAN CLASS="Symbol">
l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
. Thus, for example, a 1.5<SPAN CLASS="Symbol">
 m</SPAN>
m technology should have a cell density of roughly (1/1.5)<SUP CLASS="Superscript">
2</SUP>
 gates/mil<SUP CLASS="Superscript">
2</SUP>
. How does this agree with your estimate for the LSI Logic array?</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=137284">
 </A>
3.25&nbsp;<A NAME="13514">
 </A>
(SiArc RAM, 10 min.) Suppose we need 16<SPAN CLASS="Symbol">
 </SPAN>
k-bit of SRAM and 20<SPAN CLASS="Symbol">
 </SPAN>
k-gate of random logic on a channelless gate array. Assume a base cell with four transistors and that we can build a RAM cell using two of these base cells. The RAM bits will require 32k base cells and the random logic will require 20k base cells. Suppose the base cell area is 12 tracks high, 3 tracks wide, and the horizontal and vertical track spacing is equal at 8<SPAN CLASS="Symbol">
l</SPAN>
. </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=211221">
 </A>
a.&nbsp;Calculate the total area of the base cells we need. Now suppose we redesign the gate-array base cell so that we can build a RAM bit cell using a single base cell that is 20 tracks high, 3 tracks wide, and has 4 logic cell transistors and 4 RAM cell transistors. Assume that since the base cell now contains 8 transistors we only need 12<SPAN CLASS="Symbol">
 </SPAN>
k base cells to implement 20<SPAN CLASS="Symbol">
 </SPAN>
k-gate of random logic (the new base cell is less efficient than the old cell for implementing random logic). </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=211222">
 </A>
b.&nbsp;Calculate the base cell area using the new base cell design. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=211223">
 </A>
c.&nbsp;Comment. </LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=159360">
 </A>
<SPAN CLASS="Emphasis">
Answer:</SPAN>
 1.2 <SPAN CLASS="Symbol">
&#165;</SPAN>
 108 <SPAN CLASS="Symbol">
 l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
, 1.1 <SPAN CLASS="Symbol">
&#165;</SPAN>
 108 <SPAN CLASS="Symbol">
 l</SPAN>
<SUP CLASS="Superscript">
2</SUP>
.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=136700">
 </A>
3.26&nbsp;<A NAME="39498">
 </A>
(***Gate-array base cell, 60 min.) Figure&nbsp;<A HREF="#29440" CLASS="XRef">
3.28</A>
 shows a simple gate-array base cell. Use the design rules shown in Table&nbsp;2.16 (Problem 2.33) to calculate the minimum size of this base cell. Do this by determining which design rules apply to the labels shown adjacent to each space or width in the figure. In most cases each of the spaces is determined by a single rule related to the region labeled, for example, the contact width labeled 'cc' is 2<SPAN CLASS="Symbol">
l</SPAN>
 determined by rule C.1, the exact contact size. There is one exception, shown in the figure. Space 'aa' (bounding box, BB, to edge of pdiff) and width 'bb' (edge of pdiff to edge of contact) are determined by the minimum space labeled 'xx' (bounding box, BB, to poly edge) and width 'yy' (edge of poly to edge of contact). Space 'xx' is one half of the poly to poly spacing over field (rule P.4) because two base cells abut as shown in the figure. Width 'yy' is equal to the minimum poly overlap of contact (rule C.3). The distance 'aa<SPAN CLASS="Symbol">
 </SPAN>
+<SPAN CLASS="Symbol">
 </SPAN>
bb' is thus determined by the minimum distance 'xx<SPAN CLASS="Symbol">
 </SPAN>
+<SPAN CLASS="Symbol">
 </SPAN>
yy', as shown. The other distances are more straightforward to determine. </P>
<P CLASS="Exercise">
<A NAME="pgfId=159361">
 </A>
<SPAN CLASS="Emphasis">
Answer:</SPAN>
 40<SPAN CLASS="Symbol">
 l</SPAN>
 high by 26.25<SPAN CLASS="Symbol">
 l</SPAN>
 wide.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=136779">
 </A>
<IMG SRC="CH03-47.gif" ALIGN="BASELINE">
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=136782">
 </A>
FIGURE&nbsp;3.28&nbsp;<A NAME="29440">
 </A>
<A NAME="30160">
 </A>
A simple gate-array base cell (Problem <A HREF="#39498" CLASS="XRef">
3.26</A>
).</P>
</TD>
</TR>
</TABLE>
<P CLASS="ExerciseHead">
<A NAME="pgfId=212745">
 </A>
3.27&nbsp;<A NAME="23178">
 </A>
(CIF, 15 min.) Here is the part of the CIF for a standard cell that describes the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-well (CWN) and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-well (CWP) structure. The statement <SPAN CLASS="BodyComputer">
B length height xCenter,</SPAN>
 <SPAN CLASS="BodyComputer">
yCenter</SPAN>
 is CIF for a box (CIF dimensions are in centimicrons, 0.01<SPAN CLASS="Symbol">
 m</SPAN>
m):</P>
<P CLASS="ComputerFirst">
<A NAME="pgfId=212747">
 </A>
DS1;LCWN;B6000</P>
<P CLASS="Computer">
<A NAME="pgfId=123490">
 </A>
1560 13600,3660;B2480 60 11840,2850;B2320 60 15440,2850;LCWP;B680 60</P>
<P CLASS="ComputerLast">
<A NAME="pgfId=123491">
 </A>
13740,2730;B6000 1380 13600,2010;</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=123492">
 </A>
a.&nbsp;Draw the wells and BB. Label the dimensions in microns and <SPAN CLASS="Symbol">
l (l </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.4<SPAN CLASS="Symbol">
 m</SPAN>
m<SPAN CLASS="Symbol">
)</SPAN>
.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=123493">
 </A>
b.&nbsp;This is a double-entry cell with m2 connectors at top and bottom. For this cell library the cell AB is 3<SPAN CLASS="Symbol">
l</SPAN>
 (120&nbsp;centimicrons, determined by the well rules) inside the cell BB on all sides. What is the size of the cell AB in microns and <SPAN CLASS="Symbol">
l</SPAN>
?</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=129447">
 </A>
c.&nbsp;The vertical (m2) routing pitch (the distance between centers of adjacent vertical m2 interconnect lines) is equal to the vertical track spacing and is 8<SPAN CLASS="Symbol">
l</SPAN>
 (320&nbsp;centimicrons). How many vertical tracks are there in this cell?</LI>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=137498">
 </A>
3.28&nbsp;<A NAME="24686">
 </A>
(CIF, 60 min.) Figure&nbsp;<A HREF="#22670" CLASS="XRef">
3.29</A>
 shows an example of CIF that describes a single rectangle (box) of m1 with an accompanying label.</P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Computer">
<A NAME="pgfId=137694">
 </A>
(CIF written by the Tanner Research layout editor: L-Edit);<BR>
(TECHNOLOGY: VLSIcmn6);<BR>
(DATE: Thu, Jun 27, 1996);<BR>
(FABCELL: NONE);<BR>
(SCALING: 1 CIF Unit = 1/120 Lambda, 1 Lambda = 3/10 Microns);<BR>
DS1 2 8;<BR>
9 Cell0;<BR>
94 LabelText 60 180 CM;<BR>
LCM;<BR>
B 240 120 120 300;<BR>
DF;<BR>
E</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=137663">
 </A>
&nbsp;</P>
<DIV>
<IMG SRC="CH03-48.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=137666">
 </A>
FIGURE&nbsp;3.29&nbsp;<A NAME="22670">
 </A>
A simple CIF example (Problem <A HREF="#24686" CLASS="XRef">
3.28</A>
).</P>
</TD>
</TR>
</TABLE>
<P CLASS="Exercise">
<A NAME="pgfId=137534">
 </A>
The CIF code has the following meaning:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=137535">
 </A>
Lines 1&#8211;5 are <A NAME="marker=137863">
 </A>
CIF comments.</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=137536">
 </A>
Line 6 is a <SPAN CLASS="Definition">
definition start</SPAN>
<A NAME="marker=137862">
 </A>
 for symbol 1 and marks the beginning of a <SPAN CLASS="Definition">
symbol definition</SPAN>
<A NAME="marker=137864">
 </A>
 (a symbol is a piece of layout, symbol numbers are unique identifiers). The integers 2 and 8 define a <SPAN CLASS="Definition">
scaling factor</SPAN>
<A NAME="marker=137865">
 </A>
 2/8 (=<SPAN CLASS="Symbol">
 </SPAN>
 0.25) to be applied to distance measurements (the CIF unit, after scaling, is a <SPAN CLASS="Definition">
centimicron</SPAN>
<A NAME="marker=137866">
 </A>
 or 0.01<SPAN CLASS="Symbol">
 m</SPAN>
m).</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=137549">
 </A>
Line 7 is a <SPAN CLASS="Definition">
user extension</SPAN>
<A NAME="marker=137867">
 </A>
 or expansion (all extensions begin with a digit). L-Edit uses user extension 9 for cell names (<SPAN CLASS="BodyComputer">
Cell0</SPAN>
 in this case).</LI>
<LI CLASS="Bull