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<H1 CLASS="Heading1">
<A NAME="pgfId=224054">
</A>
3.10 <A NAME="25815">
</A>
Problems</H1>
<P CLASS="Exercise">
<A NAME="pgfId=224055">
</A>
*<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
difficult, **<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
very difficult, ***<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
extremely difficult</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=224056">
</A>
3.1 (Pull resistance, 10 min.)</P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=224018">
</A>
a. Show that, for small <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
, an <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor looks like a resistor, R = 1/(<SPAN CLASS="Symbol">
b</SPAN>
<SUB CLASS="SubscriptVariable">
n</SUB>
(<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
– V<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
)). </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=211137">
</A>
b. If <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
, <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
0, and <SPAN CLASS="Symbol">
</SPAN>
k<SUP CLASS="Superscript">
'</SUP>
<SUB CLASS="Subscript">
n</SUB>
=<SPAN CLASS="Symbol">
</SPAN>
200<SPAN CLASS="Symbol">
m</SPAN>
AV<SUP CLASS="Superscript">
–2</SUP>
(equal to the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor SPICE parameter <SPAN CLASS="BodyComputer">
KP</SPAN>
in Table 2.1), find the pull resistance, <SPAN CLASS="EquationVariables">
R</SPAN>
, for a 6/0.6 transistor in the linear region.</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=161365">
</A>
<SPAN CLASS="Emphasis">
Answer: </SPAN>
(b) 213<SPAN CLASS="Symbol">
W</SPAN>
.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=223984">
</A>
3.2 (Inversion layer depth, 15 min.) In the absence of surface charge, Gauss’s law demands continuity of the electric displacement vector, <SPAN CLASS="Vector">
D</SPAN>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
e</SPAN>
<SPAN CLASS="Vector">
E</SPAN>
, at the silicon surface, so that <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
ox</SUB>
<SPAN CLASS="EquationVariables">
E</SPAN>
<SUB CLASS="Subscript">
ox</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
Si</SUB>
<SPAN CLASS="EquationVariables">
E</SPAN>
<SUB CLASS="Subscript">
Si</SUB>
, where <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
ox</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
3.9, <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
Si</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
11.7. </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=223985">
</A>
a. Assuming the potential at the surface is <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
<SPAN CLASS="Symbol">
</SPAN>
–<SPAN CLASS="Symbol">
</SPAN>
V<SUB CLASS="Subscript">
t</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
2.5<SPAN CLASS="Symbol">
</SPAN>
V, calculate <SPAN CLASS="EquationVariables">
E</SPAN>
<SUB CLASS="Subscript">
ox</SUB>
and <SPAN CLASS="EquationVariables">
E</SPAN>
<SUB CLASS="Subscript">
Si</SUB>
if T<SUB CLASS="Subscript">
ox</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
100<SPAN CLASS="Symbol">
</SPAN>
Å. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=211139">
</A>
b. Assume that carrier density <SPAN CLASS="Symbol">
∝</SPAN>
exp<SPAN CLASS="Symbol">
</SPAN>
(–q<SPAN CLASS="Symbol">
f</SPAN>
/kT), where <SPAN CLASS="Symbol">
f</SPAN>
is the potential; calculate the distance below the surface at which the inversion charge density falls to 10<SPAN CLASS="Symbol">
</SPAN>
percent of its value at the surface. </LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=211140">
</A>
c. Comment on the accuracy of your answers.</LI>
</UL>
<P CLASS="Exercise">
<A NAME="pgfId=186178">
</A>
<SPAN CLASS="Emphasis">
Answer: </SPAN>
(a) 2.5<SPAN CLASS="Symbol">
¥ </SPAN>
10<SUP CLASS="Superscript">
8</SUP>
<SPAN CLASS="Symbol">
</SPAN>
Vm<SUP CLASS="Superscript">
–1</SUP>
, 0.833<SPAN CLASS="Symbol">
¥ </SPAN>
10<SUP CLASS="Superscript">
8</SUP>
<SPAN CLASS="Symbol">
</SPAN>
Vm<SUP CLASS="Superscript">
–1</SUP>
. (b) 7.16<SPAN CLASS="Symbol">
</SPAN>
Å.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=186050">
</A>
3.3 (Depletion layer depth, 15 min.) The depth of the depletion region under the gate is given by <SPAN CLASS="EquationVariables">
x</SPAN>
<SUB CLASS="SubscriptVariable">
d</SUB>
= <SPAN CLASS="Symbol">
÷[</SPAN>
(2<SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
Si</SUB>
<SPAN CLASS="Symbol">
f</SPAN>
<SUB CLASS="SubscriptVariable">
s</SUB>
)/(qN<SUB CLASS="Subscript">
A</SUB>
)], where <SPAN CLASS="Symbol">
f</SPAN>
<SUB CLASS="SubscriptVariable">
s</SUB>
= 2V<SUB CLASS="Subscript">
T</SUB>
ln(N<SUB CLASS="Subscript">
A</SUB>
/n<SUB CLASS="Subscript">
i</SUB>
) is the surface potential at strong inversion. Calculate <SPAN CLASS="Symbol">
f</SPAN>
<SUB CLASS="SubscriptVariable">
s</SUB>
and <SPAN CLASS="EquationVariables">
x</SPAN>
<SUB CLASS="SubscriptVariable">
d</SUB>
assuming: <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
Si</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=1.0359<SPAN CLASS="Symbol">
¥ </SPAN>
10<SUP CLASS="Superscript">
–10</SUP>
<SPAN CLASS="Symbol">
</SPAN>
Fm<SUP CLASS="Superscript">
–1</SUP>
, the substrate doping, N<SUB CLASS="Subscript">
A</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
1.4<SPAN CLASS="Symbol">
¥ </SPAN>
10<SUP CLASS="Superscript">
17</SUP>
<SPAN CLASS="Symbol">
</SPAN>
cm<SUP CLASS="Superscript">
–3</SUP>
, the <SPAN CLASS="Definition">
intrinsic carrier concentration</SPAN>
<A NAME="marker=186165">
</A>
n<SUB CLASS="Subscript">
i</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
1.45<SPAN CLASS="Symbol">
¥ </SPAN>
10<SUP CLASS="Superscript">
10</SUP>
<SPAN CLASS="Symbol">
</SPAN>
cm<SUP CLASS="Superscript">
–3</SUP>
(at room temperature), and the thermal voltage V<SUB CLASS="Subscript">
T</SUB>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
kT/q<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
25.9<SPAN CLASS="Symbol">
</SPAN>
mV.</P>
<P CLASS="Exercise">
<A NAME="pgfId=186113">
</A>
<SPAN CLASS="Emphasis">
Answer:</SPAN>
0.833<SPAN CLASS="Symbol">
</SPAN>
V, 900<SPAN CLASS="Symbol">
</SPAN>
Å.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=185946">
</A>
3.4 (Logical effort, 45 min.) Calculate the logical effort at each input of an AOI122 cell. Find an expression that allows you to calculate the logical effort for each input of an AOI<SPAN CLASS="EquationVariables">
nnnn</SPAN>
cell for <SPAN CLASS="EquationVariables">
n</SPAN>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
1, 2, 3.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=16011">
</A>
3.5 (Gate-array macro design, 120 min.) Draw a 1X drive, two-input NAND cell using the gate-array base cells shown in Figures <A HREF="CH03.6.htm#11168" CLASS="XRef">
3.14</A>
(a)–<A HREF="CH03.6.htm#39811" CLASS="XRef">
3.16</A>
(lay a piece of thin paper over the figures and draw the contacts and metal personalization only). Label the inputs and outputs. Lay out a 1X drive, four-input NAND cell using the same base array cells. Now lay out a 2X drive, four-input NAND cell (think about this one). Make sure that you size your transistors properly to balance rise times and fall times.</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=15952">
</A>
3.6 <A NAME="13646">
</A>
(Flip-flop library, 20 min.) Suppose we wish to build a library of flip-flops. We want to have flops with: positive-edge and negative-edge triggering: clear, preset (either, both, or neither); synchronous or asynchronous reset and preset controls if present (but not mixed on the same flip-flop); all flip-flops with or without scan as an option; flip-flops with Q and Qbar (either or both). How many flip-flops is that? (***) How would you attempt to prioritize which flip-flops to include in a library?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=106073">
</A>
3.7 <A NAME="10403">
</A>
(AOI and OAI cell ratios, 30 min.) In Figure 2.13(c) we adjusted the sizes of the transistors assuming that there was only one path through the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel stacks. Suppose that <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistors A, B, C, and D are all on and <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor E turns on. What is the equivalent resistance of the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel stack in this case?</P>
<P CLASS="ExerciseHead">
<A NAME="pgfId=40963">
</A>
3.8 <A NAME="33502">
</A>
(**Eight-input AND, 60 min.) This question is an example in the paper by Sutherland and Sproull [1991] on logical effort. Figure <A HREF="#31737" CLASS="XRef">
3.24</A>
shows three different ways to design an eight-input AND cell, using NAND and NOR cells. </P>
<UL>
<LI CLASS="ExercisePartFirst">
<A NAME="pgfId=40899">
</A>
a. Find the logical effort at each input for A, B, C. Assume a logic ratio of 2.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=54685">
</A>
b. Find the parasitic delay for A, B, C. Assume the parasitic delay of an inverter is 0.6.</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=86159">
</A>
c. Show that the path delays are given by the following equations where <SPAN CLASS="EquationVariables">
H </SPAN>
is the path electrical effort, if we ignore the nonideal delays:</LI>
<LI CLASS="ExcerciseList">
<A NAME="pgfId=109292">
</A>
(i) 2<SPAN CLASS="Symbol">
</SPAN>
(3.33<SPAN CLASS="EquationVariables">
H</SPAN>
)<SUP CLASS="Superscript">
0.5</SUP>
<SPAN CLASS="Symbol">
</SPAN>
+<SPAN CLASS="Symbol">
</SPAN>
5.4 (alternative A)</LI>
<LI CLASS="ExcerciseList">
<A NAME="pgfId=211170">
</A>
(ii) 2<SPAN CLASS="Symbol">
</SPAN>
(3.33<SPAN CLASS="EquationVariables">
H</SPAN>
)<SUP CLASS="Superscript">
0.5</SUP>
<SPAN CLASS="Symbol">
</SPAN>
+<SPAN CLASS="Symbol">
</SPAN>
3.6 (alternative B)</LI>
<LI CLASS="ExcerciseList">
<A NAME="pgfId=211173">
</A>
(iii) 4<SPAN CLASS="Symbol">
</SPAN>
(2.96<SPAN CLASS="EquationVariables">
H</SPAN>
)<SUP CLASS="Superscript">
0.25</SUP>
<SPAN CLASS="Symbol">
</SPAN>
+<SPAN CLASS="Symbol">
</SPAN>
4.2 (alternative C)</LI>
<LI CLASS="ExercisePart">
<A NAME="pgfId=109310">
</A>
d. Use these equations to determine the best alternative for <SPAN CLASS="EquationVariables">
H</SPAN>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
2 and <SPAN CLASS="EquationVariables">
H</SPAN>
<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
32.</LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigTitleSide">
<A NAME="pgfId=148785">
</A>
FIGURE 3.24 <A NAME="31737">
</A>
An eight-input AND cell (Problem <A HREF="#33502" CLASS="XRef">
3.8</A>
).</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=148790">
</A>
<IMG SRC="CH03-42.gif" ALIGN="BASELINE">
</P>
</TD>
</TR>
</TABLE>
</UL>
<P CLASS="ExerciseHead">
<A NAME="pgfId=54669">
</A>
3.9 (Special logic cells, 30 min.) Many ASIC cell libraries contain “special” logic cells. For example the Compass libraries contain a two-input NAND cell with an inverted input, FN01 = (A<SPAN CLASS="Symbol">
</SPAN>
+<SPAN CLASS="Symbol">
</SPAN>
B'). This saves routing area, is faster than using two separate cells, and is useful because the combination of a two-input NAND gate with one inverted input is heavily used by synthesis tools. Other “special” cells include:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=148827">
</A>
FN02<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
MAJ3<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
(A·B<SPAN CLASS="Symbol">
</SPAN>
+<SPAN CLASS="Symbol">
</SPAN>
A·C<SPAN CLASS="Symbol">
</SPAN>
+<SPAN CLASS="Symbol">
</SPAN>
B·C)'</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=54673">
</A>
FN03<SPAN CLASS="Symbol">
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