ch03.2.htm

介绍asci设计的一本书

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3.2.4&nbsp;Input Slew Rate</H3>
<P CLASS="BodyAfterHead">
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Figure&nbsp;<A HREF="#14939" CLASS="XRef">
3.6</A>
 shows an experiment to monitor the input capacitance of an inverter as it switches. We have introduced another variable&#8212;the delay of the input ramp or the <A NAME="marker=202021">
 </A>
slew rate of the input.</P>
<P CLASS="Body">
<A NAME="pgfId=202046">
 </A>
In Figure&nbsp;<A HREF="#14939" CLASS="XRef">
3.6</A>
(b) the input ramp is 40<SPAN CLASS="Symbol">
 </SPAN>
ps long with a slew rate of 3<SPAN CLASS="Symbol">
 </SPAN>
V/ 40<SPAN CLASS="Symbol">
 </SPAN>
ps or 75<SPAN CLASS="Symbol">
 </SPAN>
GVs<SUP CLASS="Superscript">
&#8211;1</SUP>
&#8212;as in our previous experiments&#8212;and the output of the inverter hardly moves before the input has changed. The input capacitance varies from 20 to 40<SPAN CLASS="Symbol">
 </SPAN>
fF with an average value of approximately 34<SPAN CLASS="Symbol">
 </SPAN>
fF for both transitions&#8212;we can measure the average value in Probe by plotting <SPAN CLASS="BodyComputer">
AVG(-i(Vin))</SPAN>
. </P>
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<P CLASS="Table">
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 </A>
<SPAN CLASS="Bold">
(a)</SPAN>
</P>
<DIV>
<IMG SRC="CH03-11.gif">
</DIV>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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(b)</P>
<DIV>
<IMG SRC="CH03-12.gif">
</DIV>
</TD>
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<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="Table">
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 </A>
<SPAN CLASS="Bold">
(c)</SPAN>
</P>
<DIV>
<IMG SRC="CH03-13.gif">
</DIV>
</TD>
</TR>
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<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFigTitleSide">
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 </A>
FIGURE&nbsp;3.6&nbsp;<A NAME="14939">
 </A>
 The input capacitance of an inverter. (a)&nbsp;Input capacitance is measured by monitoring the input current to the inverter, <SPAN CLASS="BodyComputer">
i(Vin)</SPAN>
. (b)&nbsp;Very fast switching. The current, <SPAN CLASS="BodyComputer">
i(Vin)</SPAN>
, is multiplied by the input ramp delay (<SPAN CLASS="Symbol">
D</SPAN>
<SPAN CLASS="EquationVariables">
t</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.04<SPAN CLASS="Symbol">
 </SPAN>
ns) and divided by the voltage swing (<SPAN CLASS="Symbol">
D</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
3<SPAN CLASS="Symbol">
 </SPAN>
V) to give the equivalent input capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
<SPAN CLASS="EquationVariables">
i</SPAN>
<SPAN CLASS="Symbol">
 D</SPAN>
<SPAN CLASS="EquationVariables">
t</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
/<SPAN CLASS="Symbol">
 D</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
. Thus an adjusted input current of 40<SPAN CLASS="Symbol">
 </SPAN>
fA corresponds to an input capacitance of 40<SPAN CLASS="Symbol">
 </SPAN>
fF. The current, <SPAN CLASS="BodyComputer">
i(Vin)</SPAN>
, is positive for the rising edge of the input and negative for the falling edge. (c)&nbsp;Very slow switching. The input capacitance is now equal for both transitions.</P>
</TD>
</TR>
</TABLE>
<P CLASS="Body">
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In Figure&nbsp;<A HREF="#14939" CLASS="XRef">
3.6</A>
(c) the input ramp is slow enough (300<SPAN CLASS="Symbol">
 </SPAN>
ns) that we are switching under almost equilibrium conditions&#8212;at each voltage we allow the output to find its level on the static transfer curve of Figure&nbsp;<A HREF="CH03.1.htm#34786" CLASS="XRef">
3.2</A>
(a). The switching waveforms are quite different. The average input capacitance is now approximately 0.04<SPAN CLASS="Symbol">
 </SPAN>
pF (a 20<SPAN CLASS="Symbol">
 </SPAN>
percent difference). The propagation delay (using an input trip point of 0.5 and an output trip point of 0.35) is negative and approximately 150<SPAN CLASS="Symbol">
 </SPAN>
&#8211;<SPAN CLASS="Symbol">
 </SPAN>
127<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
&#8211;23<SPAN CLASS="Symbol">
 </SPAN>
ns. By changing the input slew rate we have broken our model. For the moment we shall ignore this problem and proceed. </P>
<P CLASS="Body">
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The calculations in Table&nbsp;<A HREF="#38143" CLASS="XRef">
3.1</A>
 and behavior of Figures&nbsp;<A HREF="#16486" CLASS="XRef">
3.5</A>
 and <A HREF="#14939" CLASS="XRef">
3.6</A>
 are very complex. How can we find the value of the parasitic capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
, to fit the model of Figure&nbsp;<A HREF="CH03.1.htm#33981" CLASS="XRef">
3.1</A>
? Once again, as we did for pull resistance and the intrinsic output capacitance, instead of trying to derive a theoretical value for <SPAN CLASS="EquationVariables">
C, </SPAN>
we adjust the value to fit the model. Before we formulate another experiment we should bear in mind the following questions that the experiment of Figure<A HREF="#14939" CLASS="XRef">
3.6</A>
 raises: Is it valid to replace the nonlinear input capacitance with a linear component? Is it valid to use a linear input ramp when the normal waveforms are so nonlinear?</P>
<P CLASS="Body">
<A NAME="pgfId=187039">
 </A>
Figure&nbsp;<A HREF="#37711" CLASS="XRef">
3.7</A>
 shows an experiment crafted to answer these questions. The experiment has the following two steps:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=186887">
 </A>
Adjust <SPAN CLASS="BodyComputer">
c2</SPAN>
 to model the input capacitance of <SPAN CLASS="BodyComputer">
m5/6</SPAN>
; then <SPAN CLASS="EquationVariables">
C</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
<SPAN CLASS="BodyComputer">
c2</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.0335<SPAN CLASS="Symbol">
 </SPAN>
pF.</LI>
<LI CLASS="NumberLast">
<A NAME="pgfId=186888">
 </A>
Remove all the parasitic capacitances for inverter <SPAN CLASS="BodyComputer">
m9/10</SPAN>
&#8212;except for the gate capacitances <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
GD</SUB>
, and <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
GB</SUB>
&#8212;and then adjust <SPAN CLASS="BodyComputer">
c3</SPAN>
 (0.01<SPAN CLASS="Symbol">
 </SPAN>
pF) and <SPAN CLASS="BodyComputer">
c4</SPAN>
 (0.025<SPAN CLASS="Symbol">
 </SPAN>
pF) to model the effect of these missing parasitics.</LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=186551">
 </A>
<SPAN CLASS="Bold">
(a)</SPAN>
</P>
<DIV>
<IMG SRC="CH03-14.gif">
</DIV>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=186556">
 </A>
<SPAN CLASS="Bold">
(c)</SPAN>
</P>
<DIV>
<IMG SRC="CH03-15.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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(b)</P>
<DIV>
<IMG SRC="CH03-16.gif">
</DIV>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
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(d)</P>
<DIV>
<IMG SRC="CH03-17.gif">
</DIV>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="2">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=186562">
 </A>
FIGURE&nbsp;3.7&nbsp;<A NAME="37711">
 </A>
Parasitic capacitance. (a)&nbsp;All devices in this circuit include parasitic capacitance. (b)&nbsp;This circuit uses linear capacitors to model the parasitic capacitance of <SPAN CLASS="BodyComputer">
m9/10</SPAN>
. The load formed by the inverter (<SPAN CLASS="BodyComputer">
m5</SPAN>
 and <SPAN CLASS="BodyComputer">
m6</SPAN>
) is modeled by a 0.0335<SPAN CLASS="Symbol">
 </SPAN>
pF capacitor (<SPAN CLASS="BodyComputer">
c2</SPAN>
); the parasitic capacitance due to the overlap of the gates of <SPAN CLASS="BodyComputer">
m3</SPAN>
 and <SPAN CLASS="BodyComputer">
m4</SPAN>
 with their source, drain, and bulk terminals is modeled by a 0.01<SPAN CLASS="Symbol">
 </SPAN>
pF capacitor (<SPAN CLASS="BodyComputer">
c3</SPAN>
); and the effect of the parasitic capacitance at the drain terminals of <SPAN CLASS="BodyComputer">
m3</SPAN>
 and <SPAN CLASS="BodyComputer">
m4</SPAN>
 is modeled by a 0.025<SPAN CLASS="Symbol">
 </SPAN>
pF capacitor (<SPAN CLASS="BodyComputer">
c4</SPAN>
). (c)&nbsp;The two circuits compared. The delay shown (1.22<SPAN CLASS="Symbol">
 </SPAN>
&#8211;<SPAN CLASS="Symbol">
 </SPAN>
1.135<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.085<SPAN CLASS="Symbol">
 </SPAN>
ns) is equal to<SPAN CLASS="EquationVariables">
 t</SPAN>
<SUB CLASS="SubscriptVariable">
PDf</SUB>
 for the inverter <SPAN CLASS="BodyComputer">
m3/4</SPAN>
. (d)&nbsp;An exact match would have both waveforms equal at the 0.35 trip point (1.05<SPAN CLASS="Symbol">
 </SPAN>
V).</P>
</TD>
</TR>
</TABLE>
</OL>
<P CLASS="Body">
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We can summarize our findings from this and previous experiments as follows:</P>
<OL>
<LI CLASS="NumberFirst">
<A NAME="pgfId=188113">
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Since the waveforms in Figure&nbsp;<A HREF="#37711" CLASS="XRef">
3.7</A>
 match, we can model the input capacitance of a logic cell with a linear capacitor. However, we know the input capacitance may vary (by up to 20<SPAN CLASS="Symbol">
 </SPAN>
percent in our example) with the input slew rate.</LI>
<LI CLASS="NumberList">
<A NAME="pgfId=221423">
 </A>
The input waveform to the inverter <SPAN CLASS="BodyComputer">
m3/m4</SPAN>
 in Figure&nbsp;<A HREF="#37711" CLASS="XRef">
3.7</A>
 is from another inverter&#8212;not a linear ramp. The difference in slew rate causes an error. The measured delay is 85<SPAN CLASS="Symbol">
 </SPAN>
ps (0.085<SPAN CLASS="Symbol">
 </SPAN>
ns), whereas our model (Eq.&nbsp;<A HREF="CH03.1.htm#33563" CLASS="XRef">
3.7</A>
) predicts  </LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=221429">
 </A>
<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PDr</SUB>
 = (38 + 817 <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
out</SUB>
) ps = ( 38 + (817)&#183;(0.0355) ) ps = 65 ps .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
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 </A>
(3.8)</P>
</TD>
</TR>
</TABLE>
<LI CLASS="NumberList">
<A NAME="pgfId=188276">
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The total gate-oxide capacitance in our inverter with T<SUB CLASS="Subscript">
ox</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
100&Aring; is  </LI>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=258866">
 </A>
C<SUB CLASS="Subscript">
O</SUB>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=221856">
 </A>
= (W<SUB CLASS="SubscriptVariable">
n</SUB>
L<SUB CLASS="SubscriptVariable">
n</SUB>
 + W<SUB CLASS="SubscriptVariable">
p</SUB>
L<SUB CLASS="SubscriptVariable">
p</SUB>
)<SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
ox</SUB>
 T<SUB CLASS="Subscript">
ox</SUB>
 </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=221858">
 </A>
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=258868">
 </A>
&nbsp;</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqn">
<A NAME="pgfId=221860">
 </A>
= (34.5 <SPAN CLASS="Symbol">
&#165;</SPAN>
 10<SUP CLASS="Superscript">
&#8211;4</SUP>
)&#183;(6)&#183;( (0.6) + (12)&#183;(0.6) ) pF = 0.037 pF .</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnNumber">
<A NAME="pgfId=221862">
 </A>
<A NAME="17748">
 </A>
(3.9)</P>
</TD>
</TR>
</TABLE>
<LI CLASS="NumberList">
<A NAME="pgfId=188221">
 </A>
All the transistor parasitic capacitances excluding the gate capacitance contribute 0.01<SPAN CLASS="Symbol">
 </SPAN>
pF of the 0.0335<SPAN CLASS="Symbol">
 </SPAN>
pF input capacitance&#8212;about 30 percent. The gate capacitances contribute the rest&#8212;0.025<SPAN CLASS="Symbol">
 </SPAN>
pF (about 70  percent).</LI>
</OL>
<P CLASS="Body">
<A NAME="pgfId=317271">
 </A>
The last two observations are useful. Since the gate capacitances are nonlinear, we only see about 0.025/0.037 or 70  percent of the 0.037<SPAN CLASS="Symbol">
 </SPAN>
pF gate-oxide capacitance, C<SUB CLASS="Subscript">
O</SUB>
, in the input capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
. This means that it happens by chance that the total gate-oxide capacitance is also a rough estimate of the gate input capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SPAN CLASS="Symbol">
 &#170; </SPAN>
C<SUB CLASS="Subscript">
O</SUB>
. Using L and W rather than L<SUB CLASS="Subscript">
EFF</SUB>
 and W<SUB CLASS="Subscript">
EFF</SUB>
 in Eq.&nbsp;<A HREF="#17748" CLASS="XRef">
3.9</A>
 helps this estimate. The accuracy of this estimate depends on the fact that the junction capacitances are approximately one-third of the gate-oxide capacitance&#8212;which happens to be true for many CMOS processes for the shapes of transistors that normally occur in logic cells. In the next section we shall use this estimate to help us design logic cells.</P>
</DIV>
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