ch03.2.htm

介绍asci设计的一本书

.MODEL CMOSN NMOS LEVEL=3 PHI=0.7 TOX=10E-09 XJ=0.2U TPG=1 VTO=0.65 DELTA=0.7<BR>
+ LD=5E-08 KP=2E-04 UO=550 THETA=0.27 RSH=2 GAMMA=0.6 NSUB=1.4E+17 NFS=6E+11<BR>
+ VMAX=2E+05 ETA=3.7E-02 KAPPA=2.9E-02 CGDO=3.0E-10 CGSO=3.0E-10 CGBO=4.0E-10<BR>
+ CJ=5.6E-04 MJ=0.56 CJSW=5E-11 MJSW=0.52 PB=1<BR>
m1  out1 in1 0 0 cmosn W=6U L=0.6U AS=7.2P AD=7.2P PS=8.4U PD=8.4U</P>
</TD>
</TR>
</TABLE>
<DIV>
<H3 CLASS="Heading2">
<A NAME="pgfId=185127">
 </A>
3.2.1&nbsp;Junction Capacitance</H3>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=185405">
 </A>
The junction capacitances, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
BD</SUB>
 and <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
BS</SUB>
, consist of two parts: junction area and sidewall; both have different physical characteristics with parameters: <SPAN CLASS="BodyComputer">
CJ</SPAN>
 and <SPAN CLASS="BodyComputer">
MJ </SPAN>
for the junction, <SPAN CLASS="BodyComputer">
CJSW</SPAN>
 and <SPAN CLASS="BodyComputer">
MJSW</SPAN>
 for the sidewall, and <SPAN CLASS="BodyComputer">
PB</SPAN>
 is common. These capacitances depend on the voltage across the junction (<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DB</SUB>
 and <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
SB</SUB>
). The calculations in Table&nbsp;<A HREF="#38143" CLASS="XRef">
3.1</A>
 assume both source and drain regions are 6<SPAN CLASS="Symbol">
 m</SPAN>
m<SPAN CLASS="Symbol">
 &#165; </SPAN>
1.2<SPAN CLASS="Symbol">
 m</SPAN>
m rectangles, so that A<SUB CLASS="Subscript">
D</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
A<SUB CLASS="Subscript">
S</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
7.2<SPAN CLASS="Symbol">
 </SPAN>
(<SPAN CLASS="Symbol">
m</SPAN>
m)<SUP CLASS="Superscript">
2</SUP>
, and the perimeters (excluding the 1.2<SPAN CLASS="Symbol">
 m</SPAN>
m channel edge) are P<SUB CLASS="Subscript">
D</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
P<SUB CLASS="Subscript">
S</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
6<SPAN CLASS="Symbol">
 </SPAN>
+<SPAN CLASS="Symbol">
 </SPAN>
1.2<SPAN CLASS="Symbol">
 </SPAN>
+<SPAN CLASS="Symbol">
 </SPAN>
1.2<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
8.4<SPAN CLASS="Symbol">
 m</SPAN>
m. We exclude the channel edge because the sidewalls facing the channel (corresponding to <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
BSJ</SUB>
<SUB CLASS="Subscript">
GATE</SUB>
 and <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
BDJ</SUB>
<SUB CLASS="Subscript">
GATE</SUB>
 in Figure&nbsp;<A HREF="#17045" CLASS="XRef">
3.4</A>
) are different from the sidewalls that face the field. There is no standard method to allow for this. It is a mistake to exclude the gate edge assuming it is accounted for in the rest of the model&#8212;it is not. A pessimistic simulation includes the channel edge in P<SUB CLASS="Subscript">
D</SUB>
 and P<SUB CLASS="Subscript">
S</SUB>
  (but a true worst-case analysis would use more accurate models and worst-case model parameters). In HSPICE there is a separate mechanism to account for the channel edge capacitance (using parameters <SPAN CLASS="BodyComputer">
ACM</SPAN>
<A NAME="marker=185457">
 </A>
<A NAME="marker=185458">
 </A>
 and <A NAME="marker=185417">
 </A>
<SPAN CLASS="BodyComputer">
CJGATE</SPAN>
). In Table&nbsp;<A HREF="#38143" CLASS="XRef">
3.1</A>
 we have neglected <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
J</SUB>
<SUB CLASS="Subscript">
GATE</SUB>
.</P>
<P CLASS="Body">
<A NAME="pgfId=185126">
 </A>
For the <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor <SPAN CLASS="BodyComputer">
m2</SPAN>
 (W<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
12<SPAN CLASS="Symbol">
 m</SPAN>
m and L<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.6<SPAN CLASS="Symbol">
 m</SPAN>
m) the source and drain regions are 12<SPAN CLASS="Symbol">
 m</SPAN>
m<SPAN CLASS="Symbol">
 &#165; </SPAN>
1.2<SPAN CLASS="Symbol">
 m</SPAN>
m rectangles, so that A<SUB CLASS="Subscript">
D</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
A<SUB CLASS="Subscript">
S</SUB>
<SPAN CLASS="Symbol">
 &#170; </SPAN>
14<SPAN CLASS="Symbol">
 </SPAN>
(<SPAN CLASS="Symbol">
m</SPAN>
m)<SUP CLASS="Superscript">
2</SUP>
, and the perimeters are P<SUB CLASS="Subscript">
D</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
P<SUB CLASS="Subscript">
S</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
12<SPAN CLASS="Symbol">
 </SPAN>
+<SPAN CLASS="Symbol">
 </SPAN>
1.2<SPAN CLASS="Symbol">
 </SPAN>
+<SPAN CLASS="Symbol">
 </SPAN>
1.2 <SPAN CLASS="Symbol">
&#170; </SPAN>
14<SPAN CLASS="Symbol">
 m</SPAN>
m (these parameters are rounded to two significant figures solely to simplify the figures and tables).</P>
<P CLASS="Body">
<A NAME="pgfId=187530">
 </A>
In passing, notice that a 1.2<SPAN CLASS="Symbol">
 m</SPAN>
m strip of diffusion in a 0.6<SPAN CLASS="Symbol">
 m</SPAN>
m process (<SPAN CLASS="Symbol">
l </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.3<SPAN CLASS="Symbol">
 m</SPAN>
m) is only 4 <SPAN CLASS="Symbol">
 l</SPAN>
 wide&#8212;wide enough to place a contact only with aggressive spacing rules. The conservative rules in Figure&nbsp;2.11 would require a diffusion width of at least 2<SPAN CLASS="Symbol">
 </SPAN>
(rule 6.4a)<SPAN CLASS="Symbol">
 </SPAN>
+<SPAN CLASS="Symbol">
 </SPAN>
2<SPAN CLASS="Symbol">
 </SPAN>
(rule 6.3a)<SPAN CLASS="Symbol">
 </SPAN>
+<SPAN CLASS="Symbol">
 </SPAN>
1.5<SPAN CLASS="Symbol">
 </SPAN>
(rule 6.2a)<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
5.5<SPAN CLASS="Symbol">
 l</SPAN>
.</P>
</DIV>
<DIV>
<H3 CLASS="Heading2">
<A NAME="pgfId=184782">
 </A>
3.2.2&nbsp;Overlap Capacitance</H3>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=185132">
 </A>
The overlap capacitance calculations for C<SUB CLASS="Subscript">
GSOV</SUB>
 and C<SUB CLASS="Subscript">
GDOV</SUB>
 in Table&nbsp;<A HREF="#38143" CLASS="XRef">
3.1</A>
 account for lateral diffusion (the amount the source and drain extend under the gate) using SPICE parameter <SPAN CLASS="BodyComputer">
LD</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
<SPAN CLASS="BodyComputer">
=</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
<SPAN CLASS="BodyComputer">
5E-08</SPAN>
 or L<SUB CLASS="Subscript">
D</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0.05<SPAN CLASS="Symbol">
 m</SPAN>
m. Not all versions of SPICE use the equivalent parameter for width reduction, <SPAN CLASS="BodyComputer">
WD</SPAN>
 (assumed zero in Table&nbsp;<A HREF="#38143" CLASS="XRef">
3.1</A>
), in calculating C<SUB CLASS="Subscript">
GDOV</SUB>
 and not all versions subtract W<SUB CLASS="Subscript">
D</SUB>
 to form W<SUB CLASS="Subscript">
EFF</SUB>
. </P>
</DIV>
<DIV>
<H3 CLASS="Heading2">
<A NAME="pgfId=185133">
 </A>
3.2.3&nbsp;Gate Capacitance</H3>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=185134">
 </A>
The gate capacitance calculations in Table&nbsp;<A HREF="#38143" CLASS="XRef">
3.1</A>
 depend on the operating region. The gate&#8211;source capacitance <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
 varies from zero when the transistor is off to 0.5C<SUB CLASS="Subscript">
O</SUB>
 (0.5<SPAN CLASS="Symbol">
 &#165; </SPAN>
1.035<SPAN CLASS="Symbol">
 &#165; </SPAN>
10<SUP CLASS="Superscript">
&#8211;15</SUP>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
5.18<SPAN CLASS="Symbol">
 &#165; </SPAN>
10<SUP CLASS="Superscript">
&#8211;16</SUP>
<SPAN CLASS="Symbol">
 </SPAN>
F) in the linear region to (2/3)C<SUB CLASS="Subscript">
O</SUB>
 in the saturation region (6.9<SPAN CLASS="Symbol">
 &#165; </SPAN>
10<SUP CLASS="Superscript">
&#8211;16</SUP>
<SPAN CLASS="Symbol">
 </SPAN>
F). The gate&#8211;drain capacitance <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
GD</SUB>
 varies from zero (off) to 0.5C<SUB CLASS="Subscript">
O</SUB>
 (linear region) and back to zero (saturation region).</P>
<P CLASS="Body">
<A NAME="pgfId=185898">
 </A>
The gate&#8211;bulk capacitance <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
GB</SUB>
 may be viewed as two capacitors in series: the fixed gate-oxide capacitance, C<SUB CLASS="Subscript">
O</SUB>
 =<SPAN CLASS="Symbol">
 </SPAN>
W<SUB CLASS="Subscript">
EFF</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
L<SUB CLASS="Subscript">
EFF</SUB>
<SPAN CLASS="Symbol">
  e</SPAN>
<SUB CLASS="Subscript">
ox</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
/<SPAN CLASS="Symbol">
 </SPAN>
T<SUB CLASS="Subscript">
ox</SUB>
, and the variable depletion capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
S</SUB>
 =<SPAN CLASS="Symbol">
 </SPAN>
W<SUB CLASS="Subscript">
EFF</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
L<SUB CLASS="Subscript">
EFF</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
 <SPAN CLASS="Symbol">
e</SPAN>
<SUB CLASS="Subscript">
Si</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
 /<SPAN CLASS="Symbol">
 </SPAN>
<SPAN CLASS="EquationVariables">
x</SPAN>
<SUB CLASS="SubscriptVariable">
d</SUB>
, formed by the depletion region that extends under the gate (with varying depth <SPAN CLASS="EquationVariables">
x</SPAN>
<SUB CLASS="SubscriptVariable">
d</SUB>
). As the transistor turns on the conducting channel appears and shields the bulk from the gate&#8212;and at this point <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
GB </SUB>
falls to zero. Even with <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0<SPAN CLASS="Symbol">
 </SPAN>
V, the depletion width under the gate is finite and thus <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
GB</SUB>
<SPAN CLASS="Symbol">
 &#170; </SPAN>
4<SPAN CLASS="Symbol">
 &#165; </SPAN>
10<SUP CLASS="Superscript">
&#8211;15</SUP>
<SPAN CLASS="Symbol">
 </SPAN>
F is less than C<SUB CLASS="Subscript">
O</SUB>
<SPAN CLASS="Symbol">
 &#170; </SPAN>
10<SUP CLASS="Superscript">
&#8211;16</SUP>
<SPAN CLASS="Symbol">
 </SPAN>
F. In fact, since <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
GB</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
 <SPAN CLASS="Symbol">
&#170; </SPAN>
 0.5<SPAN CLASS="Symbol">
 </SPAN>
C<SUB CLASS="Subscript">
O</SUB>
, we can tell that at <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
0<SPAN CLASS="Symbol">
 </SPAN>
V, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
S</SUB>
<SPAN CLASS="Symbol">
 &#170; </SPAN>
C<SUB CLASS="Subscript">
O</SUB>
.</P>
<P CLASS="Body">
<A NAME="pgfId=186453">
 </A>
Figure&nbsp;<A HREF="#16486" CLASS="XRef">
3.5</A>
 shows the variation of the parasitic capacitance values. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigure">
<A NAME="pgfId=186463">
 </A>
<IMG SRC="CH03-10.gif" ALIGN="BASELINE">
&nbsp;</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFigureTitle">
<A NAME="pgfId=186466">
 </A>
FIGURE&nbsp;3.5&nbsp;<A NAME="16486">
 </A>
The variation of <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor parasitic capacitance. Values were obtained from a series of DC simulations using PSpice v5.4, the parameters shown in Table&nbsp;<A HREF="#38143" CLASS="XRef">
3.1</A>
 (<SPAN CLASS="BodyComputer">
LEVEL=3</SPAN>
), and by varying the input voltage, <SPAN CLASS="BodyComputer">
v(in1)</SPAN>
, of the inverter in Figure&nbsp;<A HREF="CH03.1.htm#19386" CLASS="XRef">
3.3</A>
(a). Data points are joined by straight lines. Note that <SPAN CLASS="BodyComputer">
CGSOV</SPAN>
<SPAN CLASS="Symbol">
 </SPAN>
=<SPAN CLASS="Symbol">
 </SPAN>
<SPAN CLASS="BodyComputer">
CGDOV</SPAN>
. </P>
</TD>
</TR>
</TABLE>
</DIV>
<DIV>
<H3 CLASS="Heading2">