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3.1 <A NAME="24209">
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Transistors as Resistors</H1>
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In Section 2.1, “CMOS Transistors,” we modeled transistors using ideal switches. If this model were accurate, logic cells would have no delay. </P>
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FIGURE 3.1 <A NAME="33981">
</A>
A model for CMOS logic delay. (a) A CMOS inverter with a load capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
out</SUB>
. (b) Input, <SPAN CLASS="BodyComputer">
v(in1)</SPAN>
, and output, <SPAN CLASS="BodyComputer">
v(out1)</SPAN>
, waveforms showing the definition of the falling propagation delay, <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PDf</SUB>
. In this case delay is measured from the input trip point of 0.5. The output trip points are 0.35 (falling) and 0.65 (rising). The model predicts <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PDf</SUB>
<SPAN CLASS="Symbol">
</SPAN>
<SPAN CLASS="Symbol">
ª </SPAN>
<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
<SPAN CLASS="Symbol">
</SPAN>
(<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
<SPAN CLASS="Symbol">
</SPAN>
+<SPAN CLASS="Symbol">
</SPAN>
<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="Subscript">
out</SUB>
). (c) The model for the inverter includes: the input capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SPAN CLASS="Symbol">
</SPAN>
; the pull-up resistance (<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pu</SUB>
) and pull-down resistance (<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
); and the parasitic output capacitance, <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
. </P>
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<P CLASS="Body">
<A NAME="pgfId=180520">
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The ramp input, <SPAN CLASS="BodyComputer">
v(in1)</SPAN>
, to the inverter in Figure <A HREF="#33981" CLASS="XRef">
3.1</A>
(a) rises quickly from zero to <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
. In response the output, <SPAN CLASS="BodyComputer">
v(out1)</SPAN>
, falls from <SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
to zero. In Figure <A HREF="#33981" CLASS="XRef">
3.1</A>
(b) we measure the <SPAN CLASS="Definition">
propagation delay</SPAN>
of the inverter, <SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PD</SUB>
, using an input trip point of 0.5 and output trip points of 0.35 (falling, <SPAN CLASS="EquationVariables">
t</SPAN>
<A NAME="marker=171562">
</A>
<SUB CLASS="SubscriptVariable">
PDf</SUB>
) and 0.65 (rising, <SPAN CLASS="EquationVariables">
t</SPAN>
<A NAME="marker=171563">
</A>
<SUB CLASS="SubscriptVariable">
PDr</SUB>
). Initially the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor, <SPAN CLASS="BodyComputer">
m1</SPAN>
, is <SPAN CLASS="Emphasis">
off</SPAN>
. As the input rises, <SPAN CLASS="BodyComputer">
m1</SPAN>
turns <SPAN CLASS="Emphasis">
on</SPAN>
in the saturation region (<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS </SUB>
<SPAN CLASS="Symbol">
</SPAN>
> <SPAN CLASS="Symbol">
</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
<SPAN CLASS="Symbol">
</SPAN>
– <SPAN CLASS="Symbol">
</SPAN>
V<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
) before entering the linear region (<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DS</SUB>
<SPAN CLASS="Symbol">
</SPAN>
< <SPAN CLASS="Symbol">
</SPAN>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
GS</SUB>
<SPAN CLASS="Symbol">
</SPAN>
– <SPAN CLASS="Symbol">
</SPAN>
V<SUB CLASS="Subscript">
t</SUB>
<SUB CLASS="SubscriptVariable">
n</SUB>
). We model transistor <SPAN CLASS="BodyComputer">
m1</SPAN>
with a resistor, <SPAN CLASS="EquationVariables">
R</SPAN>
<A NAME="marker=171560">
</A>
<SUB CLASS="SubscriptVariable">
pd</SUB>
<SPAN CLASS="EquationVariables">
</SPAN>
(Figure <A HREF="#33981" CLASS="XRef">
3.1</A>
c); this is the <SPAN CLASS="Definition">
pull-down resistance</SPAN>
<A NAME="marker=108019">
</A>
. The equivalent resistance of <SPAN CLASS="BodyComputer">
m2</SPAN>
is the <SPAN CLASS="Definition">
pull-up resistance</SPAN>
, <SPAN CLASS="EquationVariables">
R</SPAN>
<A NAME="marker=171561">
</A>
<SUB CLASS="SubscriptVariable">
pu</SUB>
.</P>
<P CLASS="Body">
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Delay is created by the pull-up and pull-down resistances, <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
and <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pu</SUB>
, together with the parasitic capacitance at the output of the cell, <SPAN CLASS="EquationVariables">
C</SPAN>
<A NAME="marker=234581">
</A>
<SUB CLASS="SubscriptVariable">
p</SUB>
(the <SPAN CLASS="Definition">
intrinsic output capacitance</SPAN>
<A NAME="marker=234582">
</A>
) and the <A NAME="marker=234583">
</A>
<SPAN CLASS="Definition">
load capacitance</SPAN>
(or <SPAN CLASS="Definition">
extrinsic output capacitance</SPAN>
<A NAME="marker=234584">
</A>
), <SPAN CLASS="EquationVariables">
C</SPAN>
<A NAME="marker=234585">
</A>
<SUB CLASS="Subscript">
out</SUB>
(Figure <A HREF="#33981" CLASS="XRef">
3.1</A>
c). If we assume a constant value for <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
, the output reaches a lower trip point of 0.35 when (Figure <A HREF="#33981" CLASS="XRef">
3.1</A>
b), </P>
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<P CLASS="TableEqnCenter">
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–<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PDf</SUB>
</P>
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<P CLASS="TableEqn">
<A NAME="pgfId=249183">
</A>
</P>
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<A NAME="pgfId=249185">
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</P>
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<P CLASS="TableEqn">
<A NAME="pgfId=249187">
</A>
0.35<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
=</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableEqnCenter">
<A NAME="pgfId=249189">
</A>
<SPAN CLASS="EquationVariables">
V</SPAN>
<SUB CLASS="SubscriptVariable">
DD</SUB>
exp</P>
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–––––––––––––––––</P>
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<P CLASS="TableEqn">
<A NAME="pgfId=249193">
</A>
.</P>
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<P CLASS="TableEqnNumber">
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(3.1)</P>
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</P>
</TD>
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<P CLASS="TableEqnCenter">
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</A>
</P>
</TD>
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<P CLASS="TableEqnCenter">
<A NAME="pgfId=249201">
</A>
<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd </SUB>
(<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
out</SUB>
+ <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
)</P>
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<P CLASS="TableEqn">
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</P>
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An output trip point of 0.35 is convenient because ln<SPAN CLASS="Symbol">
</SPAN>
(1/0.35)<SPAN CLASS="Symbol">
</SPAN>
=<SPAN CLASS="Symbol">
</SPAN>
1.04<SPAN CLASS="Symbol">
ª </SPAN>
1 and thus </P>
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<SPAN CLASS="EquationVariables">
t</SPAN>
<SUB CLASS="SubscriptVariable">
PDf </SUB>
= <SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
(<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
out</SUB>
+ <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
) ln (1/0.35) <SPAN CLASS="Symbol">
ª </SPAN>
<SPAN CLASS="EquationVariables">
R</SPAN>
<SUB CLASS="SubscriptVariable">
pd</SUB>
(<SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
out</SUB>
+ <SPAN CLASS="EquationVariables">
C</SPAN>
<SUB CLASS="SubscriptVariable">
p</SUB>
) .</P>
</TD>
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<P CLASS="TableEqnNumber">
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</A>
<A NAME="10713">
</A>
(3.2)</P>
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<P CLASS="BodyAfterHead">
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The expression for the rising delay (with a 0.65 output trip point) is identical in form. Delay thus increases linearly with the load capacitance. We often measure load capacitance in terms of a <SPAN CLASS="Definition">
standard load</SPAN>
<A NAME="marker=220831">
</A>
—the input capacitance presented by a particular cell (often an inverter or two-input NAND cell).</P>
<P CLASS="Body">
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We may adjust the delay for different trip points. For example, for output trip points of 0.1/0.9 we multiply Eq. <A HREF="#10713" CLASS="XRef">
3.2</A>
by –ln(0.1) = 2.3, because exp (–2.3) = 0.100.</P>
<P CLASS="Body">
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Figure <A HREF="#34786" CLASS="XRef">
3.2</A>
shows the DC characteristics of a CMOS inverter. To form Figure <A HREF="#34786" CLASS="XRef">
3.2</A>
(b) we take the <SPAN CLASS="EmphasisPrefix">
n</SPAN>
-channel transistor surface (Figure 2.4b) and add that for a <SPAN CLASS="EmphasisPrefix">
p</SPAN>
-channel transistor (rotated to account for the connections). Seen from above, the intersection of the two surfaces is the static transfer curve of Figure <A HREF="#34786" CLASS="XRef">
3.2</A>
(a)—along this path the transistor currents are equal and there is no output current to change the output voltage. Seen from one side, the intersection is the curve of Figure <A HREF="#34786" CLASS="XRef">
3.2</A>
(c).</P>
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<SPAN CLASS="Bold">
(a)</SPAN>
</P>
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<IMG SRC="CH03-2.gif">
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