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<H1 CLASS="Heading1">
<A NAME="pgfId=33456">
</A>
4.8 <A NAME="29892">
</A>
Summary</H1>
<P CLASS="Body">
<A NAME="pgfId=33490">
</A>
<A NAME="23541">
</A>
In this chapter we have covered FPGA programming technologies including antifuse, SRAM, and EPROM technologies; the programming technology is linked to all the other aspects of a programmable ASIC. Table <A HREF="CH04.8.htm#15424" CLASS="XRef">
4.7</A>
summarizes the programming technologies and the fabrication processes used by programmable ASIC vendors. </P>
<TABLE>
<TR>
<TD ROWSPAN="1" COLSPAN="5">
<P CLASS="TableTitle">
<A NAME="pgfId=33523">
</A>
TABLE 4.7 <A NAME="15424">
</A>
Programmable ASIC technologies.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=33535">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=33537">
</A>
<SPAN CLASS="TableHeads">
</SPAN>
</P>
<P CLASS="TableFirst">
<A NAME="pgfId=33538">
</A>
<SPAN CLASS="TableHeads">
Actel</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=33543">
</A>
<SPAN CLASS="TableHeads">
Xilinx LCA<A HREF="#pgfId=33542" CLASS="footnote">
1</A>
</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=33545">
</A>
<SPAN CLASS="TableHeads">
Altera EPLD</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableFirst">
<A NAME="pgfId=33547">
</A>
<SPAN CLASS="TableHeads">
Xilinx EPLD</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33549">
</A>
<SPAN CLASS="TableHeads">
Programming<BR>
technology</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33551">
</A>
Poly–diffusion <BR>
antifuse, PLICE</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33553">
</A>
Erasable SRAM</P>
<P CLASS="TableLeft">
<A NAME="pgfId=33554">
</A>
ISP</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33556">
</A>
UV-erasable EPROM (MAX 5k)</P>
<P CLASS="TableLeft">
<A NAME="pgfId=33557">
</A>
EEPROM (MAX 7/9k) </P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33559">
</A>
UV-erasable EPROM</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33561">
</A>
<SPAN CLASS="TableHeads">
Size of <BR>
programming<BR>
element</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33563">
</A>
Small but requires contacts to metal</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33565">
</A>
Two inverters plus pass and switch devices. Largest.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33567">
</A>
One <SPAN CLASS="EmphasisPrefix">
n</SPAN>
<SPAN CLASS="Emphasis">
-</SPAN>
channel EPROM device. </P>
<P CLASS="TableLeft">
<A NAME="pgfId=33568">
</A>
Medium.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33570">
</A>
One <SPAN CLASS="BodyComputerEmphasis">
n</SPAN>
<SPAN CLASS="Emphasis">
-</SPAN>
channel EPROM device. </P>
<P CLASS="TableLeft">
<A NAME="pgfId=33571">
</A>
Medium.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33573">
</A>
<SPAN CLASS="TableHeads">
Process</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33575">
</A>
Special: CMOS plus three extra masks.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33577">
</A>
Standard CMOS</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33579">
</A>
Standard EPROM and EEPROM</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33581">
</A>
Standard EPROM</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33583">
</A>
<SPAN CLASS="TableHeads">
Programming method</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33585">
</A>
Special hardware</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33587">
</A>
PC card, PROM, or serial port</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33589">
</A>
ISP (MAX 9k) or EPROM programmer</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33591">
</A>
EPROM programmer</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33593">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33595">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33597">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33599">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33601">
</A>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33603">
</A>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=33605">
</A>
<SPAN CLASS="TableHeads">
QuickLogic</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=33607">
</A>
<SPAN CLASS="TableHeads">
Crosspoint</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=33609">
</A>
<SPAN CLASS="TableHeads">
Atmel</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="Table">
<A NAME="pgfId=33611">
</A>
<SPAN CLASS="TableHeads">
Altera FLEX</SPAN>
</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33613">
</A>
<SPAN CLASS="TableHeads">
Programming <BR>
technology</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33615">
</A>
Metal–metal antifuse, ViaLink</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33617">
</A>
Metal–polysilicon antifuse</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33619">
</A>
Erasable SRAM.</P>
<P CLASS="TableLeft">
<A NAME="pgfId=33620">
</A>
ISP.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33622">
</A>
Erasable SRAM.</P>
<P CLASS="TableLeft">
<A NAME="pgfId=33623">
</A>
ISP.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33625">
</A>
<SPAN CLASS="TableHeads">
Size of <BR>
programming</SPAN>
</P>
<P CLASS="TableLeft">
<A NAME="pgfId=33626">
</A>
<SPAN CLASS="TableHeads">
element</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33628">
</A>
Smallest</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33630">
</A>
Small</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33632">
</A>
Two inverters plus pass and switch devices. Largest.</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33634">
</A>
Two inverters plus pass and switch devices. Largest.</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33636">
</A>
<SPAN CLASS="TableHeads">
Process</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33638">
</A>
Special, CMOS plus ViaLink</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33640">
</A>
Special, CMOS plus antifuse</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33642">
</A>
Standard CMOS</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33644">
</A>
Standard CMOS</P>
</TD>
</TR>
<TR>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33646">
</A>
<SPAN CLASS="TableHeads">
Programming method</SPAN>
</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33648">
</A>
Special hardware</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33650">
</A>
Special hardware</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33652">
</A>
PC card, PROM, or serial port</P>
</TD>
<TD ROWSPAN="1" COLSPAN="1">
<P CLASS="TableLeft">
<A NAME="pgfId=33654">
</A>
PC card, PROM, or serial port</P>
</TD>
</TR>
</TABLE>
<P CLASS="BodyAfterHead">
<A NAME="pgfId=33457">
</A>
All FPGAs have the following key elements:</P>
<UL>
<LI CLASS="BulletFirst">
<A NAME="pgfId=9686">
</A>
The programming technology</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=9687">
</A>
The basic logic cells</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=9688">
</A>
The I/O logic cells</LI>
<LI CLASS="BulletList">
<A NAME="pgfId=9689">
</A>
Programmable interconnect</LI>
<LI CLASS="BulletLast">
<A NAME="pgfId=33465">
</A>
Software to design and program the FPGA</LI>
</UL>
<HR>
<DIV CLASS="footnotes">
<DIV CLASS="footnote">
<P CLASS="TableFootnote">
<SPAN CLASS="footnoteNumber">
1.</SPAN>
<A NAME="pgfId=33542">
</A>
Lucent (formerly AT&T) FPGAs have almost identical properties to the Xilinx LCA family.</P>
</DIV>
</DIV>
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