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4.2 <A NAME="17586">
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Static RAM</H1>
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An example of <A NAME="marker=1173">
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static RAM</SPAN>
(<A NAME="marker=1176">
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SRAM</SPAN>
) programming technology is shown in <A HREF="CH04.2.htm#16065" CLASS="XRef">
Figure 4.5</A>
. This Xilinx SRAM configuration cell is constructed from two cross-coupled inverters and uses a standard CMOS process. The configuration cell drives the gates of other transistors on the chip—either turning pass transistors or transmission gates <SPAN CLASS="Emphasis">
on</SPAN>
to make a connection or <SPAN CLASS="Emphasis">
off</SPAN>
to break a connection.</P>
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FIGURE 4.5 <A NAME="16065">
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The Xilinx SRAM (static RAM) configuration cell. The outputs of the cross-coupled inverter (configuration control) are connected to the gates of pass transistors or transmission gates. The cell is programmed using the WRITE and DATA lines.</P>
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The advantages of SRAM programming technology are that designers can reuse chips during prototyping and a system can be manufactured using ISP. This programming technology is also useful for upgrades—a customer can be sent a new configuration file to reprogram a chip, not a new chip. Designers can also update or change a system on the fly in <SPAN CLASS="Definition">
reconfigurable hardware</SPAN>
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The disadvantage of using SRAM programming technology is that you need to keep power supplied to the programmable ASIC (at a low level) for the volatile SRAM to retain the connection information. Alternatively you can load the configuration data from a permanently programmed memory (typically a <A NAME="marker=24355">
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programmable read-only memory</SPAN>
or <A NAME="marker=24356">
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PROM</SPAN>
) every time you turn the system on. The total size of an SRAM configuration cell plus the transistor switch that the SRAM cell drives is also larger than the programming devices used in the antifuse technologies.</P>
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