cd11b.htm

介绍asci设计的一本书

   /******************************************************/   
   /*   module metric                                    */   
   /******************************************************/   
   /* The registers created in this module (using D flip-flops) store   
   the four path metrics. Each register is 5 bits wide. The statement   
   dff #(5) instantiates a vector array of 5 flip-flops. */   
   module metric   
         (m_in0,m_in1,m_in2,m_in3,   
         m_out0,m_out1,m_out2,m_out3,   
         clk,reset);   
   input [4:0] m_in0,m_in1,m_in2,m_in3;   
   output [4:0] m_out0,m_out1,m_out2,m_out3;   
   input clk,reset;   
      dff #(5) metric3(m_in3, m_out3, clk, reset);   
      dff #(5) metric2(m_in2, m_out2, clk, reset);   
      dff #(5) metric1(m_in1, m_out1, clk, reset);   
      dff #(5) metric0(m_in0, m_out0, clk, reset);   
   endmodule    
   /******************************************************/   
   /*   module output_decision                           */   
   /******************************************************/   
   /* This module decides the output signal based on the path that   
   corresponds to the smallest metric. The control signal comes from   
   the reduce module. */   
   module output_decision(p0,p1,p2,p3,control,out);   
      input [2:0] p0,p1,p2,p3; input [1:0] control; output [2:0] out;   
      function [2:0] decide;   
      input [2:0] p0,p1,p2,p3; input [1:0] control;   
      begin   
         if(control == 0) decide = p0;   
         else if(control == 1) decide = p1;   
         else if(control == 2) decide = p2;   
         else decide = p3;   
         end    
      endfunction   
   assign out = decide(p0,p1,p2,p3,control);   
   endmodule    
   /******************************************************/   
   /*   module reduce                                    */   
   /******************************************************/   
   /* This module reduces the metrics after the addition and compare   
   operations. This algorithm selects the smallest metric and subtracts   
   it from the other three metrics. */   
   module reduce   
         (in0,in1,in2,in3,   
         m_in0,m_in1,m_in2,m_in3,   
         control);   
      input [4:0] in0,in1,in2,in3;   
      output [4:0] m_in0,m_in1,m_in2,m_in3;   
      output [1:0] control; wire [4:0] smallest;   
      function [4:0] find_smallest;   
         input [4:0] in0,in1,in2,in3; reg [4:0] a,b;   
            begin   
               if(in0<=in1) a=in0; else a=in1;   
               if(in2<=in3) b=in2; else b=in3;   
               if(a<=b) find_smallest = a;   
               else find_smallest = b;   
            end   
      endfunction    
      function [1:0] smallest_no;   
      input [4:0] in0,in1,in2,in3,smallest;   
         begin   
            if(smallest == in0) smallest_no = 0;   
            else if (smallest == in1) smallest_no = 1;   
            else if (smallest == in2) smallest_no = 2;   
            else smallest_no = 3;   
         end   
      endfunction   
   assign smallest = find_smallest(in0,in1,in2,in3);   
   assign m_in0 = in0 - smallest;   
   assign m_in1 = in1 - smallest;   
   assign m_in2 = in2 - smallest;   
   assign m_in3 = in3 - smallest;   
   assign control = smallest_no(in0,in1,in2,in3,smallest);   
   endmodule    
   <HR ALIGN=LEFT>   
   module test_display; // display system tasks...   
   initial begin $display (&quot;string, variables, or expression&quot;);   
   /* format specifications work like printf in C...   
               %d=decimal %b=binary %s=string %h=hex %o=octal   
               %c=character %m=hierarchical name %v=strength %t=time format    
               %e=scientific %f=decimal %g=shortest   
   examples: %d uses default width %0d uses minimum width    
               %7.3g uses 7 spaces with 3 digits after decimal point */   
   // $displayb, $displayh, $displayo print in b, h, o formats   
   // $write, $strobe, $monitor also have b, h, o versions   
   $write(&quot;write&quot;); // as $display, but without newline at end of line   
   $strobe(&quot;strobe&quot;); // as $display, values at end of simulation cycle   
   $monitor(v); // disp. @change of v (except v= $time,$stime,$realtime)   
   $monitoron; $monitoroff; // toggle monitor mode on/off   
   end endmodule    
   <HR ALIGN=LEFT>   
   module file_1; integer f1, ch; initial begin f1 = $fopen(&quot;f1.out&quot;);    
   if(f1==0) $stop(2); if(f1==2)$display(&quot;f1 open&quot;);    
   ch = f1|1; $fdisplay(ch,&quot;Hello&quot;); $fclose(f1); end endmodule    
   <HR ALIGN=LEFT>   
   module load; reg [7:0] mem[0:7]; integer i; initial begin   
   $readmemb(&quot;mem.dat&quot;, mem, 1, 6); // start_address=1, end_address=6   
   for (i= 0; i&lt;8; i=i+1) $display(&quot;mem[%0d] %b&quot;, i, mem[i]);   
   end endmodule   
   <HR ALIGN=LEFT>   
   // timescale tasks...   
   module a; initial $printtimescale(b.c1); endmodule   
   module b; c c1 (); endmodule   
   `timescale 10 ns / 1 fs   
   module c_dat; endmodule   
   `timescale 1 ms / 1 ns    
   module Ttime; initial $timeformat(-9, 5, &quot; ns&quot;, 10); endmodule    
   /* $timeformat [ ( n, p, suffix , min_field_width ) ] ;   
   units = 1 second ** (-n), n=0-&gt;15, e.g. for n=9, units = ns   
   p = digits after decimal point for %t e.g. p=5 gives 0.00000   
   suffix for %t (despite timescale directive)   
   min_field_width is number of character positions for %t */   
   <HR ALIGN=LEFT>   
   module test_simulation_control; // simulation control system tasks...   
   initial begin $stop; // enter interactive mode (default parameter 1)   
   $finish(2); // graceful exit with optional parameter as follows...   
   // 0=nothing 1=time and location 2=time, location, and statistics    
   end endmodule   
   <HR ALIGN=LEFT>module timing_checks (data, clock, clock_1,clock_2);    
   input data,clock,clock_1,clock_2;reg tSU,tH,tHIGH,tP,tSK,tR;   
   specify // timing check system tasks...   
   /* $setup (data_event, reference_event, limit [, notifier]);   
   violation = (T_reference_event)-(T_data_event) &lt; limit */   
   $setup(data, posedge clock, tSU);   
   /* $hold (reference_event, data_event, limit [, notifier]);   
   violation =    
      (time_of_data_event)-(time_of_reference_event) &lt; limit */   
   $hold(posedge clock, data, tH);   
   /* $setuphold (reference_event, data_event, setup_limit,   
         hold_limit [, notifier]);   
   parameter_restriction = setup_limit + hold_limit &gt; 0 */   
   $setuphold(posedge clock, data, tSU, tH);   
   /* $width (reference_event, limit, threshold [, notifier]);   
   violation =    
      threshold &lt; (T_data_event) - (T_reference_event) &lt; limit   
   reference_event = edge   
   data_event = opposite_edge_of_reference_event */   
   $width(posedge clock, tHIGH);   
   /* $period (reference_event, limit [, notifier]);   
   violation = (T_data_event) - (T_reference_event) &lt; limit   
   reference_event = edge   
   data_event = same_edge_of_reference event */   
   $period(posedge clock, tP);   
   /* $skew (reference_event, data_event, limit [, notifier]);   
   violation = (T_data_event) - (T_reference_event) &gt; limit */   
   $skew(posedge clock_1, posedge clock_2, tSK);   
   /* $recovery (reference_event, data_event, limit, [, notifier]);   
   violation = (T_data_event) - (T_reference_event) &lt; limit */   
   $recovery(posedge clock, posedge clock_2, tR);   
   /* $nochange (reference_event, data_event, start_edge_offset,   
      end_edge_offset [, notifier]);   
   reference_event = posedge | negedge   
   violation = change while reference high (posedge)/low (negedge)   
   +ve start_edge_offset moves start of window later   
   +ve end_edge_offset moves end of window later */   
   $nochange (posedge clock, data, 0, 0);   
   endspecify endmodule    
   <HR ALIGN=LEFT>   
   primitive dff_udp(q, clock, data, notifier);   
   output q; reg q; input clock, data, notifier;   
   table //clock data notifier:state:q    
              r     0     ?    :  ?  :0 ;   
              r     1     ?    :  ?  :1 ;   
              n     ?     ?    :  ?  :- ;   
              ?     *     ?    :  ?  :- ;   
              ?     ?     *    :  ?  :x ; endtable // ...notifier   
   endprimitive   
       
   `timescale 100 fs / 1 fs    
   module dff(q, clock, data);output q; input clock, data; reg notifier;   
   dff_udp(q1, clock, data, notifier); buf(q, q1);   
   specify    
      specparam tSU = 5, tH = 1, tPW = 20, tPLH = 4:5:6, tPHL = 4:5:6;    
          (clock *&gt; q) = (tPLH, tPHL);    
      $setup(data, posedge clock, tSU, notifier); // setup: data to clock    
      $hold(posedge clock, data, tH, notifier); // hold: clock to data    
      $period(posedge clock, tPW, notifier); // clock: period   
   endspecify    
   endmodule    
   <HR ALIGN=LEFT>   
   module pla_1 (a1,a2,a3,a4,a5,a6,a7,b1,b2,b3);   
   input a1, a2, a3, a4, a5, a6, a7 ; output b1, b2, b3;   
   reg [1:7] mem[1:3]; reg b1, b2, b3;   
   initial begin   
      $readmemb(&quot;array.dat&quot;, mem);   
      #1; b1=1; b2=1; b3=1;   
      $async$and$array(mem,{a1,a2,a3,a4,a5,a6,a7},{b1,b2,b3});   
   end    
   initial $monitor(&quot;%4g&quot;,$time,,b1,,b2,,b3);   
   endmodule    
   <HR ALIGN=LEFT>   
   module pla_2; reg [1:3] a, mem[1:4]; reg [1:4] b;   
   initial begin   
      $async$and$plane(mem,{a[1],a[2],a[3]},{b[1],b[2],b[3],b[4]});   
      mem[1] = 3'b10?; mem[2] = 3'b??1; mem[3] = 3'b0?0; mem[4] = 3'b???;   
      #10 a = 3'b111; #10 $displayb(a, &quot; -&gt; &quot;, b);   
      #10 a = 3'b000; #10 $displayb(a, &quot; -&gt; &quot;, b);   
      #10 a = 3'bxxx; #10 $displayb(a, &quot; -&gt; &quot;, b);   
      #10 a = 3'b101; #10 $displayb(a, &quot; -&gt; &quot;, b);   
   end endmodule    
   <HR ALIGN=LEFT>   
   module stochastic; initial begin // stochastic analysis system tasks...   
   /* $q_initialize (q_id, q_type, max_length, status) ;   
   q_id is an integer that uniquely identifies the queue   
   q_type 1=FIFO 2=LIFO   
   max_length is an integer defining the maximum number of entries */   
   $q_initialize (q_id, q_type, max_length, status) ;   
   /* $q_add (q_id, job_id, inform_id, status) ;   
   job_id=integer input    
   inform_id= user-defined integer input for queue entry */   
   $q_add (q_id, job_id, inform_id, status) ;   
   /* $q_remove (q_id, job_id, inform_id, status) ; */   
   $q_remove (q_id, job_id, inform_id, status) ;   
   /* $q_full (q_id, status) ;   
   status = 0 = queue is not full, status = 1 = queue full */   
   $q_full (q_id, status) ;   
   /* $q_exam (q_id, q_stat_code, q_stat_value, status) ;   
   q_stat_code is input request as follows...   
   1=current queue length 2=mean inter-arrival time 3=max. queue length   
   4=shortest wait time ever    
   5=longest wait time for jobs still in queue 6=ave. wait time in queue   
   q_stat_value is output containing requested value */   
   $q_exam (q_id, q_stat_code, q_stat_value, status) ;   
   end endmodule    
   <HR ALIGN=LEFT>   
   module test_time;initial begin // simulation time system functions...   
   $time ;   
   // returns 64-bit integer scaled to timescale unit of invoking module    
   $stime ;   
   // returns 32-bit integer scaled to timescale unit of invoking module    
   $realtime ;   
   // returns real scaled to timescale unit of invoking module    
   end endmodule    
   <HR ALIGN=LEFT>   
   module test_convert; // conversion functions for reals...   
   integer i; real r; reg [63:0] bits;   
   initial begin #1 r=256;#1 i = $rtoi(r);   
   #1; r = $itor(2*i) ; #1 bits = $realtobits(2.0*r) ;   
   #1; r = $bitstoreal(bits) ; end    
   initial $monitor(&quot;%3f&quot;,$time,,i,,r,,bits); /*   
   $rtoi converts reals to integers w/truncation e.g. 123.45 -&gt; 123   
   $itor converts integers to reals e.g. 123 -&gt; 123.0   
   $realtobits converts reals to 64-bit vector    
   $bitstoreal converts bit pattern to real    
   ...real numbers in these functions conform to IEEE 754. Conversion 
      rounds to the nearest valid number. */   
   endmodule    
   <HR ALIGN=LEFT>   
   module test_real;wire [63:0]a;driver d (a);receiver r (a);   
   initial $monitor(&quot;%3g&quot;,$time,,a,,d.r1,,r.r2); endmodule   
   module driver (real_net);    
   output real_net; real r1; wire [64:1] real_net = $realtobits(r1);    
   initial #1 r1 = 123.456; endmodule    
   module receiver (real_net);    
   input real_net; wire [64:1] real_net; real r2;    
   initial assign r2 = $bitstoreal(real_net);   
   endmodule    
   <HR ALIGN=LEFT>   
   module probability; // probability distri