cd11b.htm

介绍asci设计的一本书

      #2; select = 1'bx; #2; select = 1'bz; #2; select = 1; end    
   initial $monitor("T=%2g",$time,"  Select=",select,"  Out=",out);   
   initial #10 $finish;   
   endmodule    

   module mux(a, b, mux_output, mux_select); input a, b, mux_select;   
   output mux_output; reg mux_output;   
   always begin    
   case(mux_select)   
      0: mux_output = a;   
      1: mux_output = b;   
      default mux_output = 1'bx; // if select = x or z set output to x   
   endcase    
   #1; // need some delay, otherwise we'll spin forever   
   end    
   endmodule    
   <HR ALIGN=LEFT>   
   module loop_1;   
   integer i; reg [31:0] DataBus; initial DataBus = 0;   
   initial begin    
   /************** insert loop code after here ******************/   
   /* for(execute this &lt;assignment&gt; once before starting loop; 
      exit loop if this &lt;expression&gt; is false; execute this &lt;
      assignment&gt; at end of loop before the check for end of loop) */   
   for(i=0; i&lt;=15; i=i+1) DataBus[i]=1;   
   /*************** insert loop code before here ****************/   
   end    
   initial begin   
   $display(&quot;DataBus = %b&quot;,DataBus);   
   #2; $display(&quot;DataBus = %b&quot;,DataBus); $finish;   
   end    
   endmodule    
   <HR ALIGN=LEFT>   
   module fork   
   event a,b;   
   initial    
      fork    
      @eat_breakfast; @read_paper;   
      join    
   end    
   endmodule    
   <HR ALIGN=LEFT>   
   module primitive;   
   nand (strong0, strong1) #2.2   
      Nand_1(n001, n004, n005),   
      Nand_2(n003, n001, n005, n002);   
   nand (n006, n005, n002);   
   endmodule    
   <HR ALIGN=LEFT>   
   primitive Adder(Sum, InA, InB);   
   output Sum; input Ina, InB;   
   table    
   // inputs : output   
   00 : 0;   
   01 : 1;   
   10 : 1;   
   11 : 0;   
   endtable    
   endprimitive    
   <HR ALIGN=LEFT>   
   primitive DLatch(Q, Clock, Data);   
   output Q; reg Q; input Clock, Data;   
   table    
   //inputs : present state : output (next state)   
   1 0 : ? : 0; // ? represents 0,1, or x input   
   1 1 : b : 1; // b represents 0 or 1 input   
   1 1 : x : 1; // could have combined this with previous line   
   // The following line is as it appeared in printing 1 and 2.   
   // 0 1 : ? : -; // - represents no change in an output   
   // Changed as follows by Mike Smith, 10/11/97, for printing 3.   
   0 ? : ? : -; // - represents no change in an output   
   //   
   // Explanation: I had never intended that this example to be   
   // a complete and correct model of a latch, it was meant only   
   // to illustrate UDP truth-table declaration. However, the   
   // problem with the original code (a missing truth-table   
   // specification for the case Clock=0 and Data equal to anything   
   // other than 1) looks like an error. It could cause confusion   
   // if someone was either (a) trying to figure out how this   
   // state-dependent UDP modeled a latch or (b) just blindly   
   // copied the code from the book text and used it.   
   // So, I have changed it.   
   //   
   endtable    
   endprimitive    
   <HR ALIGN=LEFT>   
   primitive DFlipFlop(Q, Clock, Data);   
   output Q; reg Q; input Clock, Data;   
   table    
   //inputs : present state : output (next state)   
   r    0 : ? : 0 ; // rising edge, next state = output = 0   
   r    1 : ? : 1 ; // rising edge, next state = output = 1   
   (0x) 0 : 0 : 0 ; // rising edge, next state = output = 0   
   (0x) 1 : 1 : 1 ; // rising edge, next state = output = 1   
   (?0) ? : ? : - ; // falling edge, no change in output   
   ? (??) : ? : - ; // no clock edge, no change in output   
   endtable    
   endprimitive    
   <HR ALIGN=LEFT>   
   module DFF_Spec; reg D, clk;   
   DFF_Part DFF1 (Q, clk, D, pre, clr);   
   initial begin D = 0; clk = 0; #1; clk = 1; end   
   initial $monitor(&quot;T=%2g&quot;,$time,&quot; clk=&quot;,clk,&quot; Q=&quot;,Q);   
   endmodule    
   module DFF_Part(Q, clk, D, pre, clr);   
      input clk, D, pre, clr; output Q;    
      DFlipFlop(Q, clk, D); // no preset or clear in this UDP   
      specify    
         specparam    
         tPLH_clk_Q = 3, tPHL_clk_Q = 2.9,   
         tPLH_set_Q = 1.2, tPHL_set_Q = 1.1;   
      (clk =&gt; Q) = (tPLH_clk_Q, tPHL_clk_Q);   
      (pre, clr *&gt; Q) = (tPLH_set_Q, tPHL_set_Q);   
      endspecify   
   endmodule    
   <HR ALIGN=LEFT>   
   `timescale 1 ns / 100 fs   
   module M_Spec; reg A1, A2, B; M M1 (Z, A1, A2, B);   
   initial begin A1=0;A2=1;B=1;#5;B=0;#5;A1=1;A2=0;B=1;#5;B=0;end   
   initial    
      $monitor(&quot;T=%4g&quot;,$realtime,&quot; A1=&quot;,A1,&quot; A2=&quot;,A2,&quot; B=&quot;,B,&quot; Z=&quot;,Z);   
   endmodule    

   `timescale 100 ps / 10 fs   
   module M(Z, A1, A2, B); input A1, A2, B; output Z;    
   or (Z1, A1, A2); nand (Z, Z1, B); // OAI21   
   /*A1 A2 B Z  delay=10*100 ps unless shown below...   
     0  0  0 1    
     0  0  1 1   
     0  1  0 1  B:0-&gt;1 Z:1-&gt;0 delay=t2   
     0  1  1 0  B:1-&gt;0 Z:0-&gt;1 delay=t1   
     1  0  0 1  B:0-&gt;1 Z:1-&gt;0 delay=t4   
     1  0  1 0  B:1-&gt;0 Z:0-&gt;1 delay=t3   
     1  1  0 1    
     1  1  1 0 */   
   specify specparam t1=11,t2=12; specparam t3=13,t4=14;    
      (A1 =&gt; Z) = 10; (A2 =&gt; Z) = 10;   
      if (~A1) (B =&gt; Z) = (t1, t2); if (A1) (B =&gt; Z) = (t3, t4);   
   endspecify    
   endmodule    
   <HR ALIGN=LEFT>   
   module Vector_And(Z,A,B);   
      parameter CARDINALITY = 1;   
      input [CARDINALITY-1:0] A,B;   
      output [CARDINALITY-1:0] Z;   
      wire [CARDINALITY-1:0] Z = A &amp; B;   
   endmodule    
   <HR ALIGN=LEFT>   
   module Four_And_Gates(OutBus, InBusA, InBusB);   
      input [3:0] InBusA, InBusB; output [3:0] OutBus;   
      Vector_And #(4) My_AND(OutBus, InBusA, InBusB); // 4 AND gates   
   endmodule    
   <HR ALIGN=LEFT>   
   module And_Gates(OutBus, InBusA, InBusB);   
      parameter WIDTH = 1;   
      input [WIDTH-1:0] InBusA, InBusB; output [WIDTH-1:0] OutBus;   
      Vector_And #(WIDTH) My_And(OutBus, InBusA, InBusB);   
   endmodule    
   module Super_Size; defparam And_Gates.WIDTH = 4; endmodule    
   <HR ALIGN=LEFT>   
   /******************************************************/   
   /* module viterbi_encode                              */   
   /******************************************************/   
   /* This is the encoder. X2N (msb) and X1N form the 2-bit input   
   message, XN. Example: if X2N=1, X1N=0, then XN=2. Y2N (msb), Y1N, and   
   Y0N form the 3-bit encoded signal, YN (for a total constellation of 8   
   PSK signals that will be transmitted). The encoder uses a state   
   machine with four states to generate the 3-bit output, YN, from the   
   2-bit input, XN. Example: the repeated input sequence XN = (X2N, X1N)   
   = 0, 1, 2, 3 produces the repeated output sequence YN = (Y2N, Y1N,   
   Y0N) = 1, 0, 5, 4. */   
   module viterbi_encode(X2N,X1N,Y2N,Y1N,Y0N,clk,res);   
   input X2N,X1N,clk,res; output Y2N,Y1N,Y0N;    
   wire X1N_1,X1N_2,Y2N,Y1N,Y0N;    
   dff dff_1(X1N,X1N_1,clk,res); dff dff_2(X1N_1,X1N_2,clk,res);    
   assign Y2N=X2N; assign Y1N=X1N ^ X1N_2; assign Y0N=X1N_1;    
   endmodule    
   <HR ALIGN=LEFT>   
   /******************************************************/   
   /* module viterbi_distances                           */   
   /******************************************************/   
   /* This module simulates the front-end of a receiver. Normally the   
   received analog signal (with noise) is converted into a series of   
   distance measures from the known eight possible transmitted PSK   
   signals: s1,...s7. We are not simulating the analog part or noise in   
   this version so we just take the digitally encoded 3-bit signal, Y,   
   from the encoder and convert it directly to the distance measures.   
   d[N] is the distance from signal=N to signal=0   
   d[N] = (2*sin(N*PI/8))**2 in 3-bit binary (on the scale 2=100)   
   Example: d[3] = 1.85**2 = 3.41 = 110   
   inN is the distance from signal=N to encoder signal.   
   Example: in3 is the distance from signal=3 to encoder signal.   
   d[N] is the distance from signal=N to encoder signal=0.   
   If encoder signal=J, shift the distances by 8-J positions.   
   Example: if signal=2, in0 is d[6], in1 is D[7], in2 is D[0], etc. */   
   module viterbi_distances   
      (Y2N,Y1N,Y0N,clk,res,in0,in1,in2,in3,in4,in5,in6,in7);   
   input clk,res,Y2N,Y1N,Y0N; output in0,in1,in2,in3,in4,in5,in6,in7;   
   reg [2:0] J,in0,in1,in2,in3,in4,in5,in6,in7; reg [2:0] d [7:0];    
   initial begin d[0]='b000;d[1]='b001;d[2]='b100;d[3]='b110;   
   d[4]='b111;d[5]='b110;d[6]='b100;d[7]='b001; end    
   always @(Y2N or Y1N or Y0N) begin   
   J[0]=Y0N;J[1]=Y1N;J[2]=Y2N;    
   J=8-J;in0=d[J];J=J+1;in1=d[J];J=J+1;in2=d[J];J=J+1;in3=d[J];   
   J=J+1;in4=d[J];J=J+1;in5=d[J];J=J+1;in6=d[J];J=J+1;in7=d[J];   
   end endmodule    
   <HR ALIGN=LEFT>
   /*****************************************************/   
   /* module viterbi_test_CDD                           */   
   /*****************************************************/   
   /* This is the top level module, viterbi_test_CDD, that models the   
   communications link. It contains three modules: viterbi_encode,   
   viterbi_distances, and viterbi. There is no analog and no noise in   
   this version. The 2-bit message, X, is encoded to a 3-bit signal, Y.   
   In this module the message X is generated using a simple counter.   
   The digital 3-bit signal Y is transmitted, received with noise as an   
   analog signal (not modeled here), and converted to a set of eight   
   3-bit distance measures, in0, ..., in7. The distance measures form   
   the input to the Viterbi decoder that reconstructs the transmitted   
   signal Y, with an error signal if the measures are inconsistent.    
   CDD = counter input, digital transmission, digital reception */   
   module viterbi_test_CDD;   
   wire Error;                              // decoder out   
   wire [2:0] Y,Out;                        // encoder out, decoder out    
   reg [1:0] X;                             // encoder inputs   
   reg Clk, Res;                            // clock and reset   
   wire [2:0] in0,in1,in2,in3,in4,in5,in6,in7;   
   always #500 $display(&quot;t    Clk X Y Out Error&quot;);   
   initial $monitor(&quot;%4g&quot;,$time,,Clk,,,,X,,Y,,Out,,,,Error);   
   initial $dumpvars; initial #3000 $finish;    
   always #50 Clk=~Clk; initial begin Clk=0;    
   X=3;                                  // no special reason to start at 3   
   #60 Res=1;#10 Res=0;end               // hit reset after inputs are stable   
   always @(posedge Clk) #1 X=X+1; // drive input with counter   
   viterbi_encode v_1   
      (X[1],X[0],Y[2],Y[1],Y[0],Clk,Res);   
   viterbi_distances v_2   
      (Y[2],Y[1],Y[0],Clk,Res,in0,in1,in2,in3,in4,in5,in6,in7);   
   viterbi v_3   
      (in0,in1,in2,in3,in4,in5,in6,in7,Out,Clk,Res,Error);   
   endmodule    
   <HR ALIGN=LEFT>   
   /******************************************************/   
   /*   module dff                                       */   
   /******************************************************/   
   /* A D flip-flop module. */   
   module dff(D,Q,Clock,Reset); // N.B. reset is active-low   
   output Q; input D,Clock,Reset;   
   parameter CARDINALITY = 1; reg [CARDINALITY-1:0] Q;   
   wire [CARDINALITY-1:0] D;   
   always @(posedge Clock) if (Reset!==0) #1 Q=D;   
   always begin wait (Reset==0); Q=0; wait (Reset==1); end    
   endmodule    
   <HR ALIGN=LEFT>   
   /* Verilog code for a Viterbi decoder. The decoder assumes a rate   
   2/3 encoder, 8 PSK modulation, and trellis coding. The viterbi module   
   contains eight submodules: subset_decode, metric, compute_metric,   
   compare_select, reduce, pathin, path_memory, and output_decision.   
      The decoder accepts eight 3-bit measures of ||r-si||**2 and, after   
   an initial delay of twelve clock cycles, the output is the best   
   estimate of the signal transmitted. The distance measures are the