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initial if (1 > 2) $stop;
// logical operators: ! (negation), && (and), || (or)
parameter B0 = !12; parameter B1 = 1 && 2;
reg [2:0] A00x; initial begin A00x = 'b111; A00x = !2'bx1; end
parameter C1 = 1 || (1/0); /* this may or may not cause an
error: the short-circuit behavior of && and || is undefined. An
evaluation including && or || may stop when an expression is known
to be true or false */
// == (logical equality), != (logical inequality)
parameter Ax = (1==1'bx); parameter Bx = (1'bx!=1'bz);
parameter D0 = (1==0); parameter D1 = (1==1);
// === case equality, !== (case inequality)
// case operators only return true or false
parameter E0 = (1===1'bx); parameter E1 = 4'b01xz === 4'b01xz;
parameter F1 = (4'bxxxx === 4'bxxxx);
// bitwise logical:
// ~ (negation), & (and), | (inclusive or),
// ^ (exclusive or), ~^ or ^~ (equivalence)
parameter A00 = 2'b01 & 2'b10;
// unary logical reduction:
// & (and), ~& (nand), | (or), ~| (nor),
// ^ (xor), ~^ or ^~ (xnor)
parameter G1= & 4'b1111;
// conditional expression x = a ? b : c
// if (a) then x = b else x = c
reg H0, a, b, c; initial begin a=1; b=0; c=1; H0=a?b:c; end
reg[2:0] J01x, Jxxx, J01z, J011;
initial begin Jxxx = 3'bxxx; J01z = 3'b01z; J011 = 3'b011;
J01x = Jxxx ? J01z : J011; end // bitwise result
initial begin #1;
$display("A10xz=%b",A10xz," A01010101=%b",A01010101);
$display("A1=%0d",A1," A2=%0d",A2," A4=%0d",A4);
$display("B1=%b",B1," B0=%b",B0," A00x=%b",A00x);
$display("C1=%b",C1," Ax=%b",Ax," Bx=%b",Bx);
$display("D0=%b",D0," D1=%b",D1);
$display("E0=%b",E0," E1=%b",E1," F1=%b",F1);
$display("A00=%b",A00," G1=%b",G1," H0=%b",H0);
$display("J01x=%b",J01x); end
endmodule
<HR ALIGN=LEFT>
module modulo; reg [2:0] Seven;
initial begin
#1 Seven = 7; #1 $display("Before=", Seven);
#1 Seven = Seven + 1; #1 $display("After =", Seven);
end
endmodule
Before=7
After =0
<HR ALIGN=LEFT>
module LRM_arithmetic;
integer IA, IB, IC, ID, IE; reg [15:0] RA, RB, RC;
initial begin
IA = -4'd12; RA = IA / 3;
RB = -4'd12; IB = RB / 3;
IC = -4'd12 / 3; RC = -12 / 3;
ID = -12 / 3; IE = IA / 3;
end
initial begin #1;
$display(" hex default");
$display("IA = -4'd12 = %h%d",IA,IA);
$display("RA = IA / 3 = %h %d",RA,RA);
$display("RB = -4'd12 = %h %d",RB,RB);
$display("IB = RB / 3 = %h%d",IB,IB);
$display("IC = -4'd12 / 3 = %h%d",IC,IC);
$display("RC = -12 / 3 = %h %d",RC,RC);
$display("ID = -12 / 3 = %h%d",ID,ID);
$display("IE = IA / 3 = %h%d",IE,IE);
end
endmodule
<HR ALIGN=LEFT>
module holiday_1(sat, sun, weekend);
input sat, sun; output weekend;
assign weekend = sat | sun;
endmodule
<HR ALIGN=LEFT>
`timescale 100s/1s // units are 100 seconds with precision of 1s
module life; wire [3:0] n; integer days;
wire wake_7am, wake_8am; // wake at 7 on weekdays else at 8
assign n = 1 + (days % 7); // n is day of the week (1-6)
always@(wake_8am or wake_7am)
$display("Day=",n," hours=%0d ",($time/36)%24," 8am = ",
wake_8am," 7am = ",wake_7am," m2.weekday = ", m2.weekday);
initial days = 0;
initial begin #(24*36*10);$finish; end // run for 10 days
always #(24*36) days = days + 1; // bump day every 24hrs
rest m1(n, wake_8am); // module instantiation
// creates a copy of module rest with instance name m1
// ports are linked using positional notation
work m2(.weekday(wake_7am), .day(n));
// creates a copy of module work with instance name m2
// ports are linked using named association
endmodule
module rest(day, weekend); // module definition
// notice the port names are different from parent
input [3:0] day; output weekend; reg weekend;
always begin #36 weekend = day > 5; end // need delay
endmodule
module work(day, weekday);
input [3:0] day; output weekday; reg weekday;
always begin #36 weekday = day < 6; end // need delay
endmodule
<HR ALIGN=LEFT>
module holiday_1(sat, sun, weekend);
input sat, sun; output weekend;
assign weekend = sat | sun; // outside a procedure
endmodule
<HR ALIGN=LEFT>
module holiday_2(sat, sun, weekend);
input sat, sun; output weekend; reg weekend;
always #1 weekend = sat | sun; // inside a procedure
endmodule
<HR ALIGN=LEFT>module assignment_1();
wire pwr_good,pwr_on,pwr_stable; reg Ok,Fire;
assign pwr_stable = Ok&(!Fire);
assign pwr_on = 1;
assign pwr_good = pwr_on & pwr_stable;
initial begin Ok=0;Fire=0; #1 Ok=1; #5 Fire=1;end
initial begin $monitor("TIME=%0d",$time," ON=",pwr_on, " STABLE=",
pwr_stable," OK=",Ok," FIRE=",Fire," GOOD=",pwr_good);
#10 $finish; end
endmodule
<HR ALIGN=LEFT>
module assignment_2; reg Enable; wire [31:0] Data;
/* the following single statement is equivalent to a declaration and
continuous assignment */
wire [31:0] DataBus = Enable ? Data : 32'bz;
assign Data = 32'b10101101101011101111000010100001;
initial begin
$monitor("Enable=%b DataBus=%b ", Enable, DataBus);
Enable = 0; #1; Enable = 1; #1; end
endmodule
<HR ALIGN=LEFT>
module always_1; reg Y, Clk;
always // statements in an always statement execute repeatedly...
begin: my_block // start of sequential block
@(posedge Clk) #5 Y = 1; // at +ve edge set Y=1
@(posedge Clk) #5 Y = 0; // at the NEXT +ve edge set Y=0
end // end of sequential block
always #10 Clk = ~ Clk; // ...we need a clock
initial Y = 0; // these initial statements execute
initial Clk = 0; // only once, but first...
initial $monitor("T=%2g",$time," Clk=",Clk," Y=",Y);
initial #70 $finish;
endmodule
<HR ALIGN=LEFT>
module procedural_assign; reg Y, A;
always @(A)
Y = A; // procedural assignment
initial begin A=0; #5; A=1; #5; A=0; #5; $finish; end
initial $monitor("T=%2g",$time,,"A=",A,,,"Y=",Y);
endmodule
<HR ALIGN=LEFT>
module delay_controls; reg X,Y,Clk,Dummy;
always #1 Dummy=!Dummy; // dummy clock, just for graphics
// examples of delay controls...
always begin #25 X=1;#10 X=0;#5; end
// an event control:
always @(posedge Clk) Y=X; // wait for +ve clock edge
always #10 Clk = !Clk; // the real clock
initial begin Clk = 0;
$display("T Clk X Y");
$monitor("%2g",$time,,,Clk,,,,X,,Y);
$dumpvars;#100 $finish; end
endmodule
<HR ALIGN=LEFT>
module show_event;
reg clock;
event event_1, event_2; // declare two named events
always @(posedge clock) -> event_1; // trigger event_1
always @ event_1
begin $display("Strike 1!!"); -> event_2; end // trigger event_2
always @ event_2 begin $display("Strike 2!!");
$finish; end // stop on detection of event_2
always #10 clock = ~ clock; // we need a clock
initial clock = 0;
endmodule
<HR ALIGN=LEFT>
module data_slip_1 (); reg Clk,D,Q1,Q2;
/************* bad sequential logic below ***************/
always @(posedge Clk) Q1 = D;
always @(posedge Clk) Q2 = Q1; // data slips here!
/************* bad sequential logic above ***************/
initial begin Clk=0; D=1; end always #50 Clk=~Clk;
initial begin $display("t Clk D Q1 Q2");
$monitor("%3g",$time,,Clk,,,,D,,Q1,,,Q2); end
initial #400 $finish; // run for 8 cycles
initial $dumpvars;
endmodule
<HR ALIGN=LEFT>
module test_dff_wait;
reg D,Clock,Reset; dff_wait u1(D,Q,Clock,Reset);
initial begin D=1;Clock=0;Reset=1'b1;#15 Reset=1'b0;#20 D=0;end
always #10 Clock=!Clock;
initial begin $display("T Clk D Q Reset");
$monitor("%2g",$time,,Clock,,,,D,,Q,,Reset); #50 $finish; end
endmodule
module dff_wait(D,Q,Clock,Reset);
output Q; input D,Clock,Reset; reg Q; wire D;
always @(posedge Clock) if (Reset!==1) Q=D;
always begin wait (Reset==1) Q=0; wait (Reset!==1); end
endmodule
<HR ALIGN=LEFT>
module dff_wait(D,Q,Clock,Reset);
output Q; input D,Clock,Reset; reg Q; wire D;
always @(posedge Clock) if (Reset!==1) Q=D;
// we need another wait statement here or we shall spin forever
always begin wait (Reset==1) Q=0; end
endmodule
<HR ALIGN=LEFT>
module delay;
reg a,b,c,d,e,f,g,bds,bsd;
initial begin
a = 1; b = 0; // no delay
#1 b = 1; // delayed assignment
c = #1 1; // intra-assignment delay
#1; //
d = 1; //
e <= #1 1; // intra-assignment, non-blocking
#1 f <= 1; // delayed non-blocking
g <= 1; // non-blocking
end
initial begin #1 bds = b; end // delay then sample (ds)
initial begin bsd = #1 b; end // sample then delay (sd)
initial begin $display("t a b c d e f g bds bsd");
$monitor("%g",$time,,a,,b,,c,,d,,e,,f,,g,,bds,,,,bsd); end
endmodule
<HR ALIGN=LEFT>
module dff_procedural_assign;
reg d,clr_,pre_,clk; wire q; dff_clr_pre dff_1(q,d,clr_,pre_,clk);
always #10 clk = ~clk;
initial begin clk = 0; clr_ = 1; pre_ = 1; d = 1;
#20; d = 0; #20; pre_ = 0; #20; pre_ = 1; #20; clr_ = 0;
#20; clr_ = 1; #20; d = 1; #20; $finish; end
initial begin
$display("T CLK PRE_ CLR_ D Q");
$monitor("%3g",$time,,,clk,,,,pre_,,,,clr_,,,,d,,q); end
endmodule
module dff_clr_pre(q,d,clear_,preset_,clock);
output q; input d,clear_,preset_,clock; reg q;
always @(clear_ or preset_)
if (!clear_) assign q = 0; // active low clear
else if(!preset_) assign q = 1; // active low preset
else deassign q;
always @(posedge clock) q = d;
endmodule
<HR ALIGN=LEFT>
module F_subset_decode; reg [2:0]A,B,C,D,E,F;
initial begin A=1;B=0;D=2;E=3;
C=subset_decode(A,B); F=subset_decode(D,E);
$display("A B C D E F");$display(A,,B,,C,,D,,E,,F); end
function [2:0] subset_decode; input [2:0] a,b;
begin if (a<=b) subset_decode=a; else subset_decode=b; end
endfunction
endmodule
<HR ALIGN=LEFT>
module test_mux; reg a,b,select; wire out;
mux mux_1(a,b,out,select);
initial begin #2; select = 0; a = 0; b = 1;
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