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`timescale 1ns/1ns
module counter;
reg clock; // declare reg data type for the clock
integer count; // declare integer data type for the count
initial // initialize things - this executes once at start
begin
clock = 0; count = 0; // initialize signals
#340 $finish; // finish after 340 time ticks
end
/* an always statement to generate the clock, only one statement
follows the always so we don't need a begin and an end */
always
#10 clock = ~ clock; // delay is set to half the clock cycle
/* an always statement to do the counting, runs at the same time
(concurrently) as the other always statement */
always
begin
// wait here until the clock goes from 1 to 0
@ (negedge clock);
// now handle the counting
if (count == 7)
count = 0;
else
count = count + 1;
$display("time = ",$time," count = ", count);
end
endmodule
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module identifiers;
/* multi-line comments in Verilog
look like C comments and // is OK in here */
// single-line comment in Verilog
reg legal_identifier,two__underscores;
reg _OK,OK_,OK_$,OK_123,CASE_SENSITIVE, case_sensitive;
reg \/clock ,\a*b ; // white_space after escaped identifier
//reg $_BAD,123_BAD; // bad names even if we declare them!
initial begin
legal_identifier =0; // embedded underscores are OK
two__underscores =0; // even two underscores in a row
_OK = 0; // identifiers can start with underscore
OK_ = 0; // and end with underscore
OK$ = 0; // $ sign is OK: beware foreign keyboards
OK_123 =0; // embedded digits are OK
CASE_SENSITIVE =0; // Verilog is case-sensitive
case_sensitive =1;
\/clock =0; // escaped identifier with \ breaks rules
\a*b =0; // but be careful! watch the spaces
$display("Variable CASE_SENSITIVE= %d",CASE_SENSITIVE);
$display("Variable case_sensitive= %d",case_sensitive);
$display("Variable \/clock = %d",\/clock );
$display("Variable \\a*b = %d",\a*b );
end
endmodule
<A NAME="anchor26554241"></A><HR ALIGN=LEFT>
module declarations_1;
wire pwr_good,pwr_on,pwr_stable; // Explicitly declare wires
integer i; // 32-bit, signed (2's complement)
time t; // 64-bit, unsigned, behaves like a 64-bit reg
event e; // Declare an event data type
real r; // Real data type of implementation defined size
// assign statement continuously drives a wire...
assign pwr_stable = 1'b1; assign pwr_on = 1; // 1 or 1'b1
assign pwr_good = pwr_on & pwr_stable;
initial begin
i = 123.456; // There must be a digit on either side
r = 123456e-3; // of the decimal point if it is present.
t = 123456e-3; // Time is rounded to 1 second by default.
$display("i=%0g",i," t=%6.2f",t," r=%f",r);
#2 $display("TIME=%0d",$time," ON=",pwr_on,
" STABLE=",pwr_stable," GOOD=",pwr_good);
$finish; end
endmodule
<A NAME="anchor26558941"></A><HR ALIGN=LEFT>
module declarations_2;
reg Q, Clk; wire D;
// drive the wire (D)
assign D = 1;
// at +ve clock edge assign the value of wire D to the reg Q:
always @(posedge Clk) Q = D;
initial Clk = 0; always #10 Clk = ~ Clk;
initial begin #50; $finish; end
always begin
$display("T=%2g", $time," D=",D," Clk=",Clk," Q=",Q); #10; end
endmodule
<A NAME="anchor26560842"></A><HR ALIGN=LEFT>
module declarations_3;
reg a,b,c,d,e;
initial begin
#10; a=0;b=0;c=0;d=0; #10; a=0;b=1;c=1;d=0;
#10; a=0;b=0;c=1;d=1; #10; $stop;
end
always begin
@(a or b or c or d) e = (a|b)&(c|d);
$display("T=%0g",$time," e=",e);
end
endmodule
<A NAME="anchor26562563"></A><HR ALIGN=LEFT>
module declarations_4;
wire Data; // a scalar net of type wire
wire [31:0] ABus, DBus; // two 32-bit wide vector wires...
// DBus[31] = left-most = most-significant bit = msb
// DBus[0] = right-most = least-significant bit = lsb
// Notice the size declaration precedes the names
// wire [31:0] TheBus, [15:0] BigBus; // illegal
reg [3:0] vector; // a 4-bit vector register
reg [4:7] nibble; // msb index < lsb index
integer i;
initial begin
i = 1;
vector = 'b1010; // vector without an index
nibble = vector; // this is OK too
#1; $display("T=%0g",$time," vector=", vector," nibble=", nibble);
#2; $display("T=%0g",$time," Bus=%b",DBus[15:0]);
end
assign DBus [1] = 1; // this is a bit-select
assign DBus [3:0] = 'b1111; // this is a part-select
// assign DBus [0:3] = 'b1111; // illegal - wrong direction
endmodule
<A NAME="anchor26564048"></A><HR ALIGN=LEFT>
module declarations_5;
reg [31:0] VideoRam [7:0]; // a 8-word by 32-bit wide memory
initial begin
VideoRam[1] = 'bxz; // must specify an index for a memory
VideoRam[2] = 1;
VideoRam[7] = VideoRam[VideoRam[2]]; // need 2 clock cycles for this
VideoRam[8] = 1; // careful! the compiler won't complain!
// Verify what we entered:
$display("VideoRam[0] is %b",VideoRam[0]);
$display("VideoRam[1] is %b",VideoRam[1]);
$display("VideoRam[2] is %b",VideoRam[2]);
$display("VideoRam[7] is %b",VideoRam[7]);
end
endmodule
<A NAME="anchor26565656"></A><HR ALIGN=LEFT>
module declarations_6;
integer Number [1:100]; // Notice that size follows name
time Time_Log [1:1000]; // - as in array of reg
// real Illegal [1:10]; // ***no real arrays***
endmodule
<A NAME="anchor26567015"></A><HR ALIGN=LEFT>
module constants;
parameter H12_UNSIZED = 'h 12; // unsized hex 12 = decimal 18
parameter H12_SIZED = 6'h 12; // sized hex 12 = decimal 18
// Notice that a space between base and value is OK
/* '' (single apostrophes) are not the same as the ' character */
parameter D42 = 8'B0010_1010; // bin 101010 = dec 42
// ...we can use underscores to increase readability.
parameter D123 = 123; // unsized decimal (default)
parameter D63 = 8'o 77; // sized octal, decimal 63
// parameter ILLEGAL = 1'o9; // no 9's in octal numbers!
/* A = 'hx and B = 'ox assume a 32 bit width */
parameter A = 'h x, B = 'o x, C = 8'b x, D = 'h z, E = 16'h ????;
// ...we can use ? instead of z, same as E = 16'h zzzz
// ...note automatic extension to 16 bits
reg [3:0] B0011,Bxxx1,Bzzz1; real R1,R2,R3; integer I1,I3,I_3;
parameter BXZ = 8'b1x0x1z0z;
initial begin
B0011 = 4'b11; Bxxx1 = 4'bx1; Bzzz1 = 4'bz1; // left padded
R1 = 0.1e1; R2 = 2.0; R3 = 30E-01; // real numbers
I1 = 1.1; I3 = 2.5; I_3 = -2.5; // IEEE rounds away from 0
end
initial begin #1;
$display
("H12_UNSIZED, H12_SIZED (hex) = %h, %h",H12_UNSIZED, H12_SIZED);
$display("D42 (bin) = %b",D42," (dec) = %d",D42);
$display("D123 (hex) = %h",D123," (dec) = %d",D123);
$display("D63 (oct) = %o",D63);
$display("A (hex) = %h",A," B (hex) = %h",B);
$display("C (hex) = %h",C," D (hex) = %h",D," E (hex) = %h",E);
$display("BXZ (bin) = %b",BXZ," (hex) = %h",BXZ);
$display("B0011, Bxxx1, Bzzz1 (bin) = %b, %b, %b",B0011,Bxxx1,Bzzz1);
$display("R1, R2, R3 (e, f, g) = %e, %f, %g", R1, R2, R3);
$display("I1, I3, I_3 (d) = %d, %d, %d", I1, I3, I_3);
end
endmodule
<A NAME="anchor26568916"></A><HR ALIGN=LEFT>
module negative_numbers;
parameter PA = -12, PB = -'d12, PC = -32'd12, PD = -4'd12;
integer IA , IB , IC , ID ; reg [31:0] RA , RB , RC , RD ;
initial begin #1;
IA = -12; IB = -'d12; IC = -32'd12; ID = -4'd12;
RA = -12; RB = -'d12; RC = -32'd12; RD = -4'd12; #1;
$display(" parameter integer reg[31:0]");
$display ("-12 =",PA,IA,,,RA);
$displayh(" ",,,,PA,,,,IA,,,,,RA);
$display ("-'d12 =",,PB,IB,,,RB);
$displayh(" ",,,,PB,,,,IB,,,,,RB);
$display ("-32'd12 =",,PC,IC,,,RC);
$displayh(" ",,,,PC,,,,IC,,,,,RC);
$display ("-4'd12 =",,,,,,,,,,PD,ID,,,RD);
$displayh(" ",,,,,,,,,,,PD,,,,ID,,,,,RD);
end
endmodule
<A NAME="anchor26570889"></A><HR ALIGN=LEFT>
module characters; /*
" is ASCII 34 (hex 22), double quote
' is ASCII 39 (hex 27), tick or apostrophe
/ is ASCII 47 (hex 2F), forward slash
\ is ASCII 92 (hex 5C), back slash
` is ASCII 96 (hex 60), accent grave
| is ASCII 124 (hex 7C), vertical bar
no standards for the graphic symbols for codes above 128...
´ is 171 (hex AB), accent acute in almost all fonts
" is 210 (hex D2), open double quote, like 66 (some fonts)
" is 211 (hex D3), close double quote, like 99 (some fonts)
' is 212 (hex D4), open single quote, like 6 (some fonts)
' is 213 (hex D5), close single quote, like 9 (some fonts)
*/ endmodule
<A NAME="anchor26573144"></A><HR ALIGN=LEFT>
module text;
parameter A_String = "abc"; // string constant, must be on one line
parameter Say = "Say \"Hey!\"";
// use escape quote \" for an embedded quote
parameter Tab = "\t"; // tab character
parameter NewLine = "\n"; // newline character
parameter BackSlash = "\\"; // back slash
parameter Tick = "\047"; // ASCII code for tick in octal
// parameter Illegal = "\500"; // illegal - no such ASCII code
initial begin
$display("A_String(str) = %s ",A_String," (hex) = %h ",A_String);
$display("Say = %s ",Say," Say \"Hey!\"");
$display("NewLine(str) = %s ",NewLine," (hex) = %h ",NewLine);
\\ Following changed in 3rd printing to clarify use of backslash
\\ $display("\(str) = %s ",BackSlash," (hex) = %h ",BackSlash);
$display("\\(str) = %s ",BackSlash," (hex) = %h ",BackSlash);
$display("Tab(str) = %s ",Tab," (hex) = %h ",Tab,"1 newline...");
$display("\n");
$display("Tick(str) = %s ",Tick," (hex) = %h ",Tick);
#1.23; $display("Time is %t", $time);
end
endmodule
<A NAME="anchor26576005"></A><HR ALIGN=LEFT>
module define;
`define G_BUSWIDTH 32 // bus width parameter (G_ for global)
/* Note: there is no semicolon at end of a compiler directive. The
character ` is ASCII 96 (hex 60), accent grave, it slopes down from
left to right. It is not the tick or apostrophe character ' (ASCII 39
or hex 27)*/
wire [`G_BUSWIDTH:0]MyBus; // 32-bit bus
endmodule
<HR ALIGN=LEFT>
module operators;
parameter A10xz = {1'b1,1'b0,1'bx,1'bz}; // concatenation
parameter A01010101 = {4{2'b01}}; // replication
// arithmetic operators: +, -, *, /, and modulus %
parameter A1 = (3+2) %2; // result of % takes sign of argument #1
// logical shift operators: << (left), >> (right)
parameter A2 = 4 >> 1; parameter A4 = 1 << 2; // zero fill
// relational operators: <, <=, >, >=
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