cd12b.htm

介绍asci设计的一本书

                case addsub is 
                  when '1'          => result_t <=          (xin + result_t); 
                  when '0'         => result_t <=          (xin - result_t);
                  when others       => result_t <=          (others => '-');
               end case;
         end if;
      end process;
end Behave_B;
<A NAME="anchor26486518"></A><HR ALIGN=LEFT>
`define resSt 0
`define S1 1
`define S2 2
`define S3 3
module StateMachine_1 (reset, clk, yOutReg);
   input reset, clk; output yOutReg;
   reg yOutReg, yOut; reg [1:0] curSt, nextSt;
   always @(posedge clk or posedge reset)
   begin:Seq //Compass statemachine oneHot curSt
      if (reset == 1) 
         begin yOut = 0; yOutReg = yOut; curSt = `resSt; end
      else begin
         case (curSt)
            `resSt:yOut = 0;`S1:yOut = 1;`S2:yOut = 1;`S3:yOut = 1;
            default:yOut = 0;
         endcase
         yOutReg = yOut; curSt = nextSt; // ... update the state.
      end
   end
   always @(curSt or yOut) // Assign the next state:
   begin:Comb 
      case (curSt)
         `resSt:nextSt = `S3;          `S1:nextSt = `S2;
         `S2:nextSt = `S1;             `S3:nextSt = `S1;
         default:nextSt = `resSt;
      endcase
   end
endmodule 
<A NAME="anchor26486519"></A><HR ALIGN=LEFT>
module StateMachine_2 (reset, clk, yOutReg);
   input reset, clk; output yOutReg; reg yOutReg, yOut; 
   parameter [1:0] //synopsys enum states 
      resSt = 2'b00, S1 = 2'b01, S2 = 2'b10, S3 = 2'b11;
   reg [1:0] /* synopsys enum states */ curSt, nextSt;
//synopsys state_vector curSt
always @(posedge clk or posedge reset) begin
   if (reset == 1) 
      begin yOut = 0; yOutReg = yOut; curSt = resSt; end
   else begin 
      case (curSt) resSt:yOut = 0;S1:yOut = 1;S2:yOut = 1;S3:yOut = 1; 
         default:yOut = 0; endcase
      yOutReg = yOut; curSt = nextSt; end
end 
always @(curSt or yOut) begin 
   case (curSt) 
   resSt:nextSt = S3; S1:nextSt = S2; S2:nextSt = S1; S3:nextSt = S1;
   default:nextSt = S1; endcase
end 
endmodule 
<A NAME="anchor26486520"></A><HR ALIGN=LEFT>
library IEEE; use IEEE.STD_LOGIC_1164.all;
entity SM1 is
   port (aIn, clk : in Std_logic; yOut: out Std_logic);
end SM1;

architecture Moore of SM1 is
   type state is (s1, s2, s3, s4);
   signal pS, nS : state;
   begin
   process (aIn, pS) begin
      case pS is
      when s1 =&gt; yOut &lt;= '0'; nS &lt;= s4;
      when s2 =&gt; yOut &lt;= '1'; nS &lt;= s3;
      when s3 =&gt; yOut &lt;= '1'; nS &lt;= s1;
      when s4 =&gt; yOut &lt;= '1'; nS &lt;= s2;
      end case;
   end process;
   process begin
      -- synopsys etc.
      --compass Statemachine adj pS
      wait until clk = '1'; pS &lt;= nS;
   end process;
end Moore;
<A NAME="anchor26486521"></A><HR ALIGN=LEFT>

dfntnb sm_ps4(.D(sm_ps1_Q),.CP(clk),.Q(sm_ps4_Q),.QN(sm_ps4_QN));
dfntnb sm_ps3(.D(sm_ps2_Q),.CP(clk),.Q(sm_ps3_Q),.QN(sm_ps3_QN));
dfntnb sm_ps2(.D(sm_ps4_Q),.CP(clk),.Q(sm_ps2_Q),.QN(sm_ps2_QN));
dfntnb sm_ps1(.D(sm_ps3_Q),.CP(clk),.Q(sm_ps1_Q),.QN(\sm_ps1.QN ));
nd03d0 i_6(.A1(sm_ps4_QN),.A2(sm_ps3_QN),.A3(sm_ps2_QN), .ZN(yout_smo));
<A NAME="anchor26486522"></A><HR ALIGN=LEFT>
dfntnb sm_ps2(.D(i_4_ZN),.CP(clk), .Q(\sm_ps2.Q ),.QN(sm_ps2_QN));
dfntnb sm_ps1(.D(sm_ps1_QN),.CP(clk),.Q(\sm_ps1.Q ),.QN(sm_ps1_QN));
oa04d1 i_4(.A1(sm_ps1_QN),.A2(sm_ps2_QN),.B(yout_smo),.ZN(i_4_ZN));
nd02d0 i_5(.A1(sm_ps2_QN), .A2(sm_ps1_QN), .ZN(yout_smo));
<A NAME="anchor26486523"></A><HR ALIGN=LEFT>
dfntnb sm_ps3(.D(i_6_ZN),.CP(clk),.Q(yout_smo),.QN(sm_ps3_QN));
dfntnb sm_ps2(.D(sm_ps3_QN),.CP(clk),.Q(sm_ps2_Q),.QN(\sm_ps2.QN ));
dfntnb sm_ps1(.D(i_5_ZN),.CP(clk),.Q(sm_ps1_Q),.QN(\sm_ps1.QN ));
nr02d0 i_5(.A1(sm_ps3_QN),.A2(sm_ps2_Q),.ZN(i_5_ZN));
nd02d0 i_6(.A1(sm_ps1_Q),.A2(yout_smo),.ZN(i_6_ZN));
<A NAME="anchor26486524"></A><HR ALIGN=LEFT>
library IEEE; use IEEE.STD_LOGIC_1164.all;
entity SM2 is
   port (aIn, clk : in Std_logic; yOut: out Std_logic);
end SM2;

architecture Mealy of SM2 is
   type state is (s1, s2, s3, s4);
   signal pS, nS : state;
   begin
   process(aIn, pS) begin
   case pS is
   when s1 =&gt; if (aIn = '1') 
      then yOut &lt;= '0'; nS &lt;= s4;
      else yOut &lt;= '1'; nS &lt;= s3;
      end if;
   when s2 =&gt; yOut &lt;= '1'; nS &lt;= s3;
   when s3 =&gt; yOut &lt;= '1'; nS &lt;= s1;
   when s4 =&gt; if (aIn = '1')
      then yOut &lt;= '1'; nS &lt;= s2;
      else yOut &lt;= '0'; nS &lt;= s1;
      end if;
   end case;
   end process;
   process begin
   wait until clk = '1' ;
   --Compass Statemachine oneHot pS
   pS &lt;= nS;
   end process;
end Mealy;
<A NAME="anchor26486525"></A><HR ALIGN=LEFT>
module RAM_1(A, CEB, WEB, OEB, INN, OUTT);
   input [6:0] A; input CEB,WEB,OEB; input [4:0]INN;
   output [4:0] OUTT; 
   reg [4:0] OUTT; reg [4:0] int_bus; reg [4:0] memory [127:0]; 
always@(negedge CEB) begin
   if (CEB == 0) begin
      if (WEB == 1) int_bus = memory[A];
      else if (WEB == 0) begin memory[A] = INN; int_bus = INN; end
      else int_bus = 5'bxxxxx;
   end
end 
always@(OEB or int_bus) begin
   case (OEB) 0 : OUTT = int_bus;
      default : OUTT = 5'bzzzzz; endcase
end 
endmodule 
<A NAME="anchor26486526"></A><HR ALIGN=LEFT>
library IEEE; 
use IEEE.STD_LOGIC_1164.all;
package RAM_package is
constant numOut : INTEGER := 8;
constant wordDepth: INTEGER := 8;
constant numAddr : INTEGER := 3;
subtype MEMV is STD_LOGIC_VECTOR(numOut-1 downto 0);
type MEM is array (wordDepth-1 downto 0) of MEMV;
end RAM_package;

library IEEE; 
use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all;
use work.RAM_package.all;
entity RAM_1 is
   port (signal A : in STD_LOGIC_VECTOR(numAddr-1 downto 0);
   signal CEB, WEB, OEB : in STD_LOGIC;
   signal INN : in  MEMV;
   signal OUTT : out MEMV);
end RAM_1;

architecture Synthesis_1 of RAM_1 is
   signal i_bus : MEMV; -- RAM internal data latch
   signal mem : MEM;  -- RAM data 
   begin
   process begin
      wait until CEB = '0';
         if WEB = '1' then i_bus &lt;= mem(TO_INTEGER(UNSIGNED(A)));
         elsif WEB = '0' then
            mem(TO_INTEGER(UNSIGNED(A))) &lt;= INN;
            i_bus &lt;= INN;
         else i_bus &lt;= (others =&gt; 'X');
         end if;
   end process;
   process(OEB, int_bus) begin -- control output drivers:
      case (OEB) is
      when '0'     =&gt; OUTT &lt;= i_bus; 
      when '1'     =&gt; OUTT &lt;= (others =&gt; 'Z');
      when others  =&gt; OUTT &lt;= (others =&gt; 'X');
      end case;
   end process;
end Synthesis_1; 
<A NAME="anchor26486527"></A><HR ALIGN=LEFT>

entity ShiftN is
   generic (TCQ:TIME := 0.3 ns; TLQ:TIME := 0.5 ns;
      TSQ:TIME := 0.7 ns);
   port(
      CLK, CLR, LD, SH, DIR: in BIT; 
      D: in BIT_VECTOR(3 downto 0);
      Q: out BIT_VECTOR(7 downto 0) );
end ShiftN;

architecture Behave of ShiftN is
   begin Shift: process (CLR, CLK)
   variable St: BIT_VECTOR(7 downto 0);
   begin
      if CLR = '1' then 
         St := (others =&gt; '0'); Q &lt;= St after TCQ;
      elsif CLK'EVENT and CLK='1' then
         if LD = '1' then 
            St := (others =&gt; '0'); 
            St(3 downto 0) := D; 
            Q &lt;= St after TLQ;
         elsif SH = '1' then
            case DIR is 
            when '0'=&gt;St:='0' &amp; St(7 downto 1);
            when '1'=&gt;St:=St(6 downto 0) &amp; '0';
            end case;
            Q &lt;= St after TSQ;
         end if;
      end if;
   end process;
end;
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architecture Behave of DFFClr is
signal Qi : BIT;
begin QB &lt;= not Qi; Q &lt;= Qi;
process (CLR, CLK) begin
   if CLR = '1' then Qi &lt;= '0' after TRQ;
   elsif CLK'EVENT and CLK = '1' then Qi &lt;= D after TCQ;
   end if;
end process;
end;
<A NAME="anchor26486529"></A><HR ALIGN=LEFT>library IEEE;use IEEE.STD_LOGIC_1164.all;use IEEE.NUMERIC_STD.all;
entity fifo_control is generic TPD:TIME := 1 ns;
   port(D_1, D_2: in UNSIGNED(11 downto 0); 
   sel : in UNSIGNED(1 downto 0) ;
   read , f1, f2, e1, e2 : in STD_LOGIC;
   r1, r2, w12:out STD_LOGIC; D: out UNSIGNED(11 downto 0);
   OE:out STD_LOGIC ) ;
end;
architecture rtl of fifo_control is
   begin process (read, sel, D_1, D_2, f1, f2, e1, e2)
   begin 
   r1 &lt;= '0' after TPD; r2 &lt;= '0' after TPD; OE_b &lt;= '0' after TPD;
   if (read = '1') then 
      w12 &lt;= '0' after TPD; 
      case sel is
      when &quot;01&quot; =&gt;          D &lt;= D_1 after TPD; r1 &lt;= '1' after TPD;
      when &quot;10&quot; =&gt;          D &lt;= D_2 after TPD; r2 &lt;= '1' after TPD;
      when &quot;00&quot; =&gt;         D(3) &lt;= f1 after TPD; D(2) &lt;= f2 after TPD;
                        D(1) &lt;= e1 after TPD; D(0) &lt;= e2 after TPD;
                        D(11 downto 4) &lt;= &quot;00000000&quot; after TPD;
      when others =&gt; OE_b &lt;= '1' after TPD; 
      end case;
   elsif (read = '0') then 
      OE_b &lt;= '0' after TPD; w12 &lt;= '1' after TPD;
   else OE_b &lt;= '0' after TPD; 
   end if;
   end process;
end rtl;
<A NAME="anchor26486530"></A><HR ALIGN=LEFT>

library COMPASS_LIB, IEEE ;
use IEEE.STD.all; use IEEE.NUMERIC_STD.all; 
use COMPASS_LIB.STDCOMP.all; use COMPASS_LIB.COMPASS.all;

entity t_control_ASIC is port(
   PadTri : out                      STD_LOGIC_VECTOR (11 downto 0) ;
   PadClk, PadInreset, PadInreadv : in      STD_LOGIC_VECTOR ( 0 downto 0) ;
   PadInp1, PadInp2 : in               STD_LOGIC_VECTOR (11 downto 0) ; 
   PadInSens : in                      STD_LOGIC_VECTOR ( 1 downto 0) ) ; 
end t_control_ASIC ;

architecture structure of t_control_ASIC is
for all : asPadIn                   use entity COMPASS_LIB.aspadIn(aspadIn) ;
for all : asPadClk                   use entity COMPASS_LIB.aspadClk(aspadClk);
for all : asPadTri                   use entity COMPASS_LIB.aspadTri(aspadTri) ;
for all : asPadVdd                   use entity COMPASS_LIB.aspadVdd(aspadVdd) ;
for all : asPadVss                   use entity COMPASS_LIB.aspadVss(aspadVss) ;
component pc3c01 port ( cclk : in STD_LOGIC; cp : out STD_LOGIC ); end component;
component t_control port(T_in1, T_in2 : in UNSIGNED(11 downto 0);
   SENSOR: in UNSIGNED( 1 downto 0) ; clk, rd, rst : in STD_LOGIC;
   D : out UNSIGNED(11 downto 0); oe_b : out STD_LOGIC ); end component ; 
signal T_in1_sv, T_in2_sv :          STD_LOGIC_VECTOR(11 downto 0) ;
signal T_in1_un, T_in2_un :          UNSIGNED(11 downto 0) ;
signal sensor_sv :                 STD_LOGIC_VECTOR(1 downto 0) ;
signal sensor_un :                 UNSIGNED(1 downto 0) ;
signal clk_sv, rd_fifo_sv, reset_sv :    STD_LOGIC_VECTOR (0 downto 0)  ;
signal clk_core, oe_b :             STD_LOGIC ;
signal D_un : UNSIGNED(11 downto 0) ; signal D_sv : STD_LOGIC_VECTOR(11 downto 0) ;
begin --compass dontTouch u* -- synopsys dont_touch etc.
u1 : asPadIn generic map(12,&quot;2:13&quot;)    port map(t_in1_sv,PadInp1) ;
u2 : asPadIn generic map(12,&quot;14:25&quot;)    port map(t_in2_sv,PadInp2) ;
u3 : asPadIn generic map(2,&quot;26:27&quot;)    port map(sensor_sv, PadInSens ) ;
u4 : asPadIn generic map(1,&quot;29&quot;)       port map(rd_fifo_sv, PadInReadv ) ;
u5 : asPadIn generic map(1,&quot;30&quot;)       port map(reset_sv, PadInreset ) ;
u6 : asPadIn generic map(1,&quot;32&quot;)       port map(clk_sv, PadClk) ;
u7 : pc3c01                      port map(clk_sv(0), clk_core) ;
u8 : asPadTri generic map(12,&quot;35:38,41:44,47:50&quot;) port map(PadTri,D_sv,oe_b);
u9 : asPadVdd generic map(&quot;1,31,34,40,45,52&quot;) port map(Vdd) ;
u10: asPadVss generic map(&quot;28,33,39,46,51,53&quot;) port map(Vss) ;
T_in1_un &lt;= UNSIGNED(T_in1_sv) ; T_in2_un &lt;= UNSIGNED(T_in2_sv) ; 
sensor_un &lt;= UNSIGNED(sensor_sv) ; D_sv &lt;= STD_LOGIC_VECTOR(D_un) ; 
v_1 : t_control port map
   (T_in1_un,T_in2_un,sensor_un, Clk_core, rd_fifo_sv(0), reset_sv(0),D_un, oe_b) ;
end;
<A NAME="anchor26486531"></A><HR ALIGN=LEFT>
`timescale 1ns / 10ps
module comp_mux_o (a, b, outp);
input  [2:0] a; input  [2:0] b;
output [2:0] outp;
supply1 VDD; supply0 VSS;

mx21d1 B1_i1 (.I0(a[0]), .I1(b[0]), .S(B1_i6_ZN), .Z(outp[0]));
oa03d1 B1_i2 (.A1(B1_i9_ZN), .A2(a[2]), .B1(a[0]), .B2(a[1]), .C(B1_i4_ZN), .ZN(B1_i2_ZN));
nd02d0 B1_i3 (.A1(a[1]), .A2(a[0]), .ZN(B1_i3_ZN));
nd02d0 B1_i4 (.A1(b[1]), .A2(B1_i3_ZN), .ZN(B1_i4_ZN));
mx21d1 B1_i5 (.I0(a[1]), .I1(b[1]), .S(B1_i6_ZN), .Z(outp[1]));
oa04d1 B1_i6 (.A1(b[2]), .A2(B1_i7_ZN), .B(B1_i2_ZN), .ZN(B1_i6_ZN));
in01d0 B1_i7 (.I(a[2]), .ZN(B1_i7_ZN));
an02d1 B1_i8 (.A1(b[2]), .A2(a[2]), .Z(outp[2]));
in01d0 B1_i9 (.I(b[2]), .ZN(B1_i9_ZN));

endmodule
<A NAME="anchor26486532"></A><HR ALIGN=LEFT>
.model comp_mux
.inputs a0 b0 a1 b1 a2 b2
.outputs outp0 outp1 outp2
.names a0 b0 a1 b1 a2 b2 sel
100000 1
101100 1
--1000 1
----10 1
100011 1
101111 1
--1011 1
.names sel a0 b0 outp0
1-1 1
01- 1
.names sel a1 b1 outp1
1-1 1
01- 1
.names sel a2 b2 outp2
1-1 1
01- 1
.exdc 
.names a0 b0 a1 b1 a2 b2 sel
000000 1
110000 1
001100 1
111100 1
000011 1
110011 1
001111 1
111111 1
.end
<A NAME="anchor26486533"></A><HR ALIGN=LEFT></PRE>
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