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assign Z = { { 2{A[1]} }, A} * { { 2{B[1]} }, B};
endmodule
<A NAME="anchor26486490"></A><HR ALIGN=LEFT>
module Counter_With_Reset (count, clock, reset);
input clock, reset; output count; reg [7:0] count;
always @ (posedge clock or negedge reset)
if (reset == 0) count = 0; else count = count + 1;
endmodule
<A NAME="anchor26486491"></A><HR ALIGN=LEFT>
module DFF_MasterSlave (D, clock, reset, Q); // D type flip-flop
input D, clock, reset; output Q; reg Q, latch;
always @(posedge clock or posedge reset)
if (reset == 1) latch = 0; else latch = D; // the master.
always @(latch) Q = latch; // the slave.
endmodule
<A NAME="anchor26486492"></A><HR ALIGN=LEFT>
module Count4(clk, reset, Q0, Q1, Q2, Q3);
input clk, reset; output Q0, Q1, Q2, Q3; wire Q0, Q1, Q2, Q3;
// Q , D , clk, reset
asDff dff0( Q0, ~Q0, clk, reset); // The asDff is a
asDff dff1( Q1, ~Q1, Q0, reset); // standard component,
asDff dff2( Q2, ~Q2, Q1, reset); // unique to one set of tools.
asDff dff3( Q3, ~Q3, Q2, reset);
endmodule
<A NAME="anchor26486493"></A><HR ALIGN=LEFT>
module asDff (D, Q, Clk, Rst);
parameter width = 1, reset_value = 0;
input [width-1:0] D; output [width-1:0] Q; reg [width-1:0] Q;
input Clk,Rst; initial Q = {width{1'bx}};
always @ ( posedge Clk or negedge Rst )
if ( Rst==0 ) Q <= #1 reset_value; else Q <= #1 D;
endmodule
<A NAME="anchor26486494"></A><HR ALIGN=LEFT>
module DP_csum(A1,B1,Z1); input [3:0] A1,B1; output Z1; reg [3:0] Z1;
always@(A1 or B1) Z1 <= A1 + B1;//Compass adder_arch cond_sum_add
endmodule
<A NAME="anchor26486495"></A><HR ALIGN=LEFT>
module DP_ripp(A2,B2,Z2); input [3:0] A2,B2; output Z2; reg [3:0] Z2;
always@(A2 or B2) Z2 <= A2 + B2;//Compass adder_arch ripple_add
endmodule
<A NAME="anchor26486496"></A><HR ALIGN=LEFT>
module DP_sub_A(A,B,OutBus,CarryIn);
input [3:0] A, B ; input CarryIn ;
output OutBus ; reg [3:0] OutBus ;
always@(A or B or CarryIn) OutBus <= A - B - CarryIn ;
endmodule
<A NAME="anchor26486497"></A><HR ALIGN=LEFT>
module DP_sub_B (A, B, CarryIn, Z) ;
input [3:0] A, B, CarryIn ; output [3:0] Z; reg [3:0] Z;
always@(A or B or CarryIn) begin
case (CarryIn)
1'b1 : Z <= A - B - 1'b1;
default : Z <= A - B - 1'b0; endcase
end
endmodule
<A NAME="anchor26486498"></A><HR ALIGN=LEFT>
entity And_Bad is port (a, b: in BIT; c: out BIT); end And_Bad;
architecture Synthesis_Bad of And_Bad is
begin process (a) -- this should be process (a, b)
begin c <= a and b;
end process;
end Synthesis_Bad;
<A NAME="anchor26486499"></A><HR ALIGN=LEFT>
entity Mux4 is port
(i: BIT_VECTOR(3 downto 0); sel: BIT_VECTOR(1 downto 0); s: out BIT);
end Mux4;
architecture Synthesis_1 of Mux4 is
begin process(sel, i) begin
case sel is
when "00" => s <= i(0); when "01" => s <= i(1);
when "10" => s <= i(2); when "11" => s <= i(3);
end case;
end process;
end Synthesis_1;
<A NAME="anchor26486500"></A><HR ALIGN=LEFT>
architecture Synthesis_2 of Mux4 is
begin with sel select s <=
i(0) when "00", i(1) when "01", i(2) when "10", i(3) when "11";
end Synthesis_2;
<A NAME="anchor26486501"></A><HR ALIGN=LEFT>
library IEEE; use ieee.std_logic_1164.all;
entity Mux8 is port
(InBus : in STD_LOGIC_VECTOR(7 downto 0);
Sel : in INTEGER range 0 to 7;
OutBit : out STD_LOGIC);
end Mux8;
architecture Synthesis_1 of Mux8 is
begin process(InBus, Sel)
variable TmpBus : STD_LOGIC_VECTOR (7 downto 0);
begin OutBit <= InBus(Sel);
end process;
end Synthesis_1;
<A NAME="anchor26486502"></A><HR ALIGN=LEFT>
library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all;
entity Decoder is port (enable : in BIT;
Din: STD_LOGIC_VECTOR (2 downto 0);
Dout: out STD_LOGIC_VECTOR (7 downto 0));
end Decoder;
architecture Synthesis_1 of Decoder is
begin
with enable select Dout <=
STD_LOGIC_VECTOR
(UNSIGNED'
(shift_left
("00000001", TO_INTEGER (UNSIGNED(Din))
)
)
)
when '1',
"11111111" when '0', "00000000" when others;
end Synthesis_1;
<A NAME="anchor26486503"></A><HR ALIGN=LEFT>
library IEEE;
use IEEE.NUMERIC_STD.all; use IEEE.STD_LOGIC_1164.all;
entity Concurrent_Decoder is port (
enable : in BIT;
Din : in STD_LOGIC_VECTOR (2 downto 0);
Dout : out STD_LOGIC_VECTOR (7 downto 0));
end Concurrent_Decoder;
architecture Synthesis_1 of Concurrent_Decoder is
begin process (Din, enable)
variable T : STD_LOGIC_VECTOR(7 downto 0);
begin
if (enable = '1') then
T := "00000000"; T( TO_INTEGER (UNSIGNED(Din))) := '1';
Dout <= T ;
else Dout <= (others => 'Z');
end if;
end process;
end Synthesis_1;
<A NAME="anchor26486504"></A><HR ALIGN=LEFT>library IEEE;
use IEEE.NUMERIC_STD.all; use IEEE.STD_LOGIC_1164.all;
entity Adder_1 is
port (A, B: in UNSIGNED(3 downto 0); C: out UNSIGNED(4 downto 0));
end Adder_1;
architecture Synthesis_1 of Adder_1 is
begin C <= ('0' & A) + ('0' & B);
end Synthesis_1;
<A NAME="anchor26486505"></A><HR ALIGN=LEFT>
library IEEE; use IEEE.STD_LOGIC_1164.all; entity DFF_With_Reset is
port(D, Clk, Reset : in STD_LOGIC; Q : out STD_LOGIC);
end DFF_With_Reset;
architecture Synthesis_1 of DFF_With_Reset is
begin process(Clk, Reset) begin
if (Reset = '0') then Q <= '0'; -- asynchronous reset
elsif rising_edge(Clk) then Q <= D;
end if;
end process;
end Synthesis_1;
architecture Synthesis_2 of DFF_With_Reset is
begin process begin
wait until rising_edge(Clk);
-- This reset is gated with the clock and is synchronous:
if (Reset = '0') then Q <= '0'; else Q <= D; end if;
end process;
end Synthesis_2;
<A NAME="anchor26486506"></A><HR ALIGN=LEFT>
`timescale 1ns/1ns
module halfgate (myInput, myOutput);
input myInput; output myOutput; wire myOutput;
assign myOutput = ~myInput;
endmodule
<A NAME="anchor26486507"></A><HR ALIGN=LEFT>
library IEEE; use IEEE.STD_LOGIC_1164.all;
library COMPASS_LIB; use COMPASS_LIB.COMPASS.all;
--compass compile_off -- synopsys etc.
use COMPASS_LIB.COMPASS_ETC.all;
--compass compile_on -- synopsys etc.
entity halfgate_u is
--compass compile_off -- synopsys etc.
generic (
myOutput_cap : Real := 0.01;
INSTANCE_NAME : string := "halfgate_u" );
--compass compile_on -- synopsys etc.
port ( myInput : in Std_Logic := 'U';
myOutput : out Std_Logic := 'U' );
end halfgate_u;
architecture halfgate_u of halfgate_u is
component in01d0
port ( I : in Std_Logic; ZN : out Std_Logic ); end component;
begin
u2: in01d0 port map ( I => myInput, ZN => myOutput );
end halfgate_u;
--compass compile_off -- synopsys etc.
library cb60hd230d;
configuration halfgate_u_CON of halfgate_u is
for halfgate_u
for u2 : in01d0 use configuration cb60hd230d.in01d0_CON
generic map (
ZN_cap => 0.0100 + myOutput_cap,
INSTANCE_NAME => INSTANCE_NAME&"/u2" )
port map ( I => I, ZN => ZN);
end for;
end for;
end halfgate_u_CON;
--compass compile_on -- synopsys etc.
<A NAME="anchor26486508"></A><HR ALIGN=LEFT>
component ASDFF
generic (WIDTH : POSITIVE := 1;
RESET_VALUE : STD_LOGIC_VECTOR := "0" );
port (Q : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
D : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
CLK : in STD_LOGIC;
RST : in STD_LOGIC );
end component;
<A NAME="anchor26486509"></A><HR ALIGN=LEFT>
library IEEE, COMPASS_LIB;
use IEEE.STD_LOGIC_1164.all; use COMPASS_LIB.STDCOMP.all;
entity Ripple_4 is
port (Trig, Reset: STD_LOGIC; QN0_5x: out STD_LOGIC;
Q : inout STD_LOGIC_VECTOR(0 to 3));
end Ripple_4;
architecture structure of Ripple_4 is
signal QN : STD_LOGIC_VECTOR(0 to 3);
component in01d1
port ( I : in Std_Logic; ZN : out Std_Logic ); end component;
component in01d5
port ( I : in Std_Logic; ZN : out Std_Logic ); end component;
begin
--compass dontTouch inv5x -- synopsys dont_touch etc.
-- Named association for hand-instantiated library cells:
inv5x: IN01D5 port map( I=>Q(0), ZN=>QN0_5x );
inv0 : IN01D1 port map( I=>Q(0), ZN=>QN(0) );
inv1 : IN01D1 port map( I=>Q(1), ZN=>QN(1) );
inv2 : IN01D1 port map( I=>Q(2), ZN=>QN(2) );
inv3 : IN01D1 port map( I=>Q(3), ZN=>QN(3) );
-- Positional association for standard components:
-- Q D Clk Rst
d0: asDFF port map(Q (0 to 0), QN(0 to 0), Trig, Reset);
d1: asDFF port map(Q (1 to 1), QN(1 to 1), Q(0), Reset);
d2: asDFF port map(Q (2 to 2), QN(2 to 2), Q(1), Reset);
d3: asDFF port map(Q (3 to 3), QN(3 to 3), Q(2), Reset);
end structure;
<A NAME="anchor26486510"></A><HR ALIGN=LEFT>
`timescale 1ns / 10ps
module ripple_4_u (trig, reset, qn0_5x, q);
input trig; input reset; output qn0_5x; inout [3:0] q;
wire [3:0] qn; supply1 VDD; supply0 VSS;
in01d5 inv5x (.I(q[0]),.ZN(qn0_5x));
in01d1 inv0 (.I(q[0]),.ZN(qn[0]));
in01d1 inv1 (.I(q[1]),.ZN(qn[1]));
in01d1 inv2 (.I(q[2]),.ZN(qn[2]));
in01d1 inv3 (.I(q[3]),.ZN(qn[3]));
dfctnb d0(.D(qn[0]),.CP(trig),.CDN(reset),.Q(q[0]),.QN(\d0.QN ));
dfctnb d1(.D(qn[1]),.CP(q[0]),.CDN(reset),.Q(q[1]),.QN(\d1.QN ));
dfctnb d2(.D(qn[2]),.CP(q[1]),.CDN(reset),.Q(q[2]),.QN(\d2.QN ));
dfctnb d3(.D(qn[3]),.CP(q[2]),.CDN(reset),.Q(q[3]),.QN(\d3.QN ));
endmodule
<A NAME="anchor26486511"></A><HR ALIGN=LEFT>
library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all;
entity SIPO_1 is port (
Clk : in STD_LOGIC;
SI : in STD_LOGIC; -- serial in
PO : buffer STD_LOGIC_VECTOR(3 downto 0)); -- parallel out
end SIPO_1;
architecture Synthesis_1 of SIPO_1 is
begin process (Clk) begin
if (Clk = '1') then PO <= SI & PO(3 downto 1); end if;
end process;
end Synthesis_1;
<A NAME="anchor26486512"></A><HR ALIGN=LEFT>
module sipo_1_u (clk, si, po);
input clk; input si; output [3:0] po;
supply1 VDD; supply0 VSS;
dfntnb po_ff_b0 (.D(po[1]),.CP(clk),.Q(po[0]),.QN(\po_ff_b0.QN));
dfntnb po_ff_b1 (.D(po[2]),.CP(clk),.Q(po[1]),.QN(\po_ff_b1.QN));
dfntnb po_ff_b2 (.D(po[3]),.CP(clk),.Q(po[2]),.QN(\po_ff_b2.QN));
dfntnb po_ff_b3 (.D(si),.CP(clk),.Q(po[3]),.QN(\po_ff_b3.QN ));
endmodule
<A NAME="anchor26486513"></A><HR ALIGN=LEFT>
library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all;
entity SIPO_R is port (
clk : in STD_LOGIC ; res : in STD_LOGIC ;
SI : in STD_LOGIC ; PO : out STD_LOGIC_VECTOR(3 downto 0));
end;
architecture Synthesis_1 of SIPO_R is
signal PO_t : STD_LOGIC_VECTOR(3 downto 0);
begin
process (PO_t) begin PO <= PO_t; end process;
process (clk, res) begin
if (res = '0') then PO_t <= (others => '0');
elsif (rising_edge(clk)) then PO_t <= SI & PO_t(3 downto 1);
end if;
end process;
end Synthesis_1;
<A NAME="anchor26486514"></A><HR ALIGN=LEFT>
library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all;
entity Adder4 is port (
in1, in2 : in BIT_VECTOR(3 downto 0) ;
mySum : out BIT_VECTOR(3 downto 0) ) ;
end Adder4;
architecture Behave_A of Adder4 is
function DIY(L,R: BIT_VECTOR(3 downto 0)) return BIT_VECTOR is
variable sum:BIT_VECTOR(3 downto 0);variable lt,rt,st,cry: BIT;
begin cry := '0';
for i in L'REVERSE_RANGE loop
lt := L(i); rt := R(i); st := lt xor rt;
sum(i):= st xor cry; cry:= (lt and rt) or (st and cry);
end loop;
return sum;
end;
begin mySum <= DIY (in1, in2); -- do it yourself (DIY) add
end Behave_A;
<A NAME="anchor26486515"></A><HR ALIGN=LEFT>
library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all;
entity Adder4 is port (
in1, in2 : in UNSIGNED(3 downto 0) ;
mySum : out UNSIGNED(3 downto 0) ) ;
end Adder4;
architecture Behave_B of Adder4 is
begin mySum <= in1 + in2; -- This uses an overloaded '+'.
end Behave_B;
<A NAME="anchor26486516"></A><HR ALIGN=LEFT>
library IEEE;
use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all;
entity Adder_Subtracter is port (
xin : in UNSIGNED(15 downto 0);
clk, addsub, clr: in STD_LOGIC;
result : out UNSIGNED(15 downto 0));
end Adder_Subtracter;
architecture Behave_A of Adder_Subtracter is
signal addout, result_t: UNSIGNED(15 downto 0);
begin
result <= result_t;
with addsub select
addout <= (xin + result_t) when '1',
(xin - result_t) when '0',
(others => '-') when others;
process (clr, clk) begin
if (clr = '0') then result_t <= (others => '0');
elsif rising_edge(clk) then result_t <= addout;
end if;
end process;
end Behave_A;
<A NAME="anchor26486517"></A><HR ALIGN=LEFT>
architecture Behave_B of Adder_Subtracter is
signal result_t: UNSIGNED(15 downto 0);
begin
result <= result_t;
process (clr, clk) begin
if (clr = '0') then result_t <= (others => '0');
elsif rising_edge(clk) then
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