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<PRE><A NAME="anchor26486443"></A><HR ALIGN=LEFT>
// comp_mux.v
module comp_mux(a, b, outp);
input [2:0] a, b;
output [2:0] outp;
function [2:0] compare;
input [2:0] ina, inb;
begin
if (ina <= inb) compare = ina;
else compare = inb;
end
endfunction
assign outp = compare(a, b);
endmodule
<A NAME="anchor26486444"></A><HR ALIGN=LEFT>
`timescale 1ns / 10ps
module comp_mux_u (a, b, outp);
input [2:0] a; input [2:0] b;
output [2:0] outp;
supply1 VDD; supply0 VSS;
in01d0 u2 (.I(b[1]), .ZN(u2_ZN));
nd02d0 u3 (.A1(a[1]), .A2(u2_ZN), .ZN(u3_ZN));
in01d0 u4 (.I(a[1]), .ZN(u4_ZN));
nd02d0 u5 (.A1(u4_ZN), .A2(b[1]), .ZN(u5_ZN));
in01d0 u6 (.I(a[0]), .ZN(u6_ZN));
nd02d0 u7 (.A1(u6_ZN), .A2(u3_ZN), .ZN(u7_ZN));
nd02d0 u8 (.A1(b[0]), .A2(u3_ZN), .ZN(u8_ZN));
nd03d0 u9 (.A1(u5_ZN), .A2(u7_ZN), .A3(u8_ZN), .ZN(u9_ZN));
in01d0 u10 (.I(a[2]), .ZN(u10_ZN));
nd02d0 u11 (.A1(u10_ZN), .A2(u9_ZN), .ZN(u11_ZN));
nd02d0 u12 (.A1(b[2]), .A2(u9_ZN), .ZN(u12_ZN));
nd02d0 u13 (.A1(u10_ZN), .A2(b[2]), .ZN(u13_ZN));
nd03d0 u14 (.A1(u11_ZN), .A2(u12_ZN), .A3(u13_ZN), .ZN(u14_ZN));
nd02d0 u15 (.A1(a[2]), .A2(u14_ZN), .ZN(u15_ZN));
in01d0 u16 (.I(u14_ZN), .ZN(u16_ZN));
nd02d0 u17 (.A1(b[2]), .A2(u16_ZN), .ZN(u17_ZN));
nd02d0 u18 (.A1(u15_ZN), .A2(u17_ZN), .ZN(outp[2]));
nd02d0 u19 (.A1(a[1]), .A2(u14_ZN), .ZN(u19_ZN));
nd02d0 u20 (.A1(b[1]), .A2(u16_ZN), .ZN(u20_ZN));
nd02d0 u21 (.A1(u19_ZN), .A2(u20_ZN), .ZN(outp[1]));
nd02d0 u22 (.A1(a[0]), .A2(u14_ZN), .ZN(u22_ZN));
nd02d0 u23 (.A1(b[0]), .A2(u16_ZN), .ZN(u23_ZN));
nd02d0 u24 (.A1(u22_ZN), .A2(u23_ZN), .ZN(outp[0]));
endmodule
<A NAME="anchor26486445"></A><HR ALIGN=LEFT>
`timescale 1ns / 10ps
module comp_mux_o (a, b, outp);
input [2:0] a; input [2:0] b;
output [2:0] outp;
supply1 VDD; supply0 VSS;
in01d0 B1_i1 (.I(a[2]), .ZN(B1_i1_ZN));
in01d0 B1_i2 (.I(b[1]), .ZN(B1_i2_ZN));
oa01d1 B1_i3 (.A1(a[0]), .A2(B1_i4_ZN), .B1(B1_i2_ZN), .B2(a[1]), .ZN(B1_i3_Z;
fn05d1 B1_i4 (.A1(a[1]), .B1(b[1]), .ZN(B1_i4_ZN));
fn02d1 B1_i5 (.A(B1_i3_ZN), .B(B1_i1_ZN), .C(b[2]), .ZN(B1_i5_ZN));
mx21d1 B1_i6 (.I0(a[0]), .I1(b[0]), .S(B1_i5_ZN), .Z(outp[0]));
mx21d1 B1_i7 (.I0(a[1]), .I1(b[1]), .S(B1_i5_ZN), .Z(outp[1]));
mx21d1 B1_i8 (.I0(a[2]), .I1(b[2]), .S(B1_i5_ZN), .Z(outp[2]));
endmodule
<A NAME="anchor26486446"></A><HR ALIGN=LEFT>
`timescale 1 ns/100 ps
module comp_mux_actel_o (a, b, outp);
input [2:0] a, b; output [2:0] outp;
wire n_13, n_17, n_19, n_21, n_23, n_27, n_29, n_31, n_62;
CM8 I_5_CM8(.D0(n_31), .D1(n_62), .D2(a[0]), .D3(n_62), .S00(n_62), .S01(n_13), .S10(n_23), .S11(n_21), .Y(outp[0]));
CM8 I_2_CM8(.D0(n_31), .D1(n_19), .D2(n_62), .D3(n_62), .S00(n_62), .S01(b[1]), .S10(n_31), .S11(n_17), .Y(outp[1]));
CM8 I_1_CM8(.D0(n_31), .D1(n_31), .D2(b[2]), .D3(n_31), .S00(n_62), .S01(n_31), .S10(n_31), .S11(a[2]), .Y(outp[2]));
VCC VCC_I(.Y(n_62));
CM8 I_4_CM8(.D0(a[2]), .D1(n_31), .D2(n_62), .D3(n_62), .S00(n_62), .S01(b[2]), .S10(n_31), .S11(a[1]), .Y(n_19));
CM8 I_7_CM8(.D0(b[1]), .D1(b[2]), .D2(n_31), .D3(n_31), .S00(a[2]), .S01(b[1]), .S10(n_31), .S11(a[1]), .Y(n_23));
CM8 I_9_CM8(.D0(n_31), .D1(n_31), .D2(a[1]), .D3(n_31), .S00(n_62), .S01(b[1]), .S10(n_31), .S11(b[0]), .Y(n_27));
CM8 I_8_CM8(.D0(n_29), .D1(n_62), .D2(n_31), .D3(a[2]), .S00(n_62), .S01(n_27), .S10(n_31), .S11(b[2]), .Y(n_13));
CM8 I_3_CM8(.D0(n_31), .D1(n_31), .D2(a[1]), .D3(n_31), .S00(n_62), .S01(a[2]), .S10(n_31), .S11(b[2]), .Y(n_17));
CM8 I_6_CM8(.D0(b[2]), .D1(n_31), .D2(n_62), .D3(n_62), .S00(n_62), .S01(a[2]), .S10(n_31), .S11(b[0]), .Y(n_21));
CM8 I_10_CM8(.D0(n_31), .D1(n_31), .D2(b[0]), .D3(n_31), .S00(n_62), .S01(n_31), .S10(n_31), .S11(a[2]), .Y(n_29));
GND GND_I(.Y(n_31));
endmodule
<A NAME="anchor26486447"></A><HR ALIGN=LEFT>
module allPads(padTri, padOut, clkOut, padBidir, padIn, padClk);
output padTri, padOut, clkOut; inout padBidir;
input [3:0] padIn; input padClk; wire [3:0] in;
//compass dontTouch u*
// asPadIn #(W, N, L, P) I (toCore, Pad) also asPadInInv
// asPadOut #(W, N, L, P) I (Pad, frCore)
// asPadTri #(W, N, S, L, P) I (Pad, frCore, OEN)
// asPadBidir #(W, N, S, L, P) I (Pad, toCore, frCore, OEN)
// asPadClk #(N, S, L) I (Clk, Pad) also asPadClkInv
// asPadVxx #(N, subnet) I (Vxx)
// W = width, integer (default=1)
// N = pin number string, e.g. "1:3,5:8"
// S = strength = {2, 4, 8, 16} in mA drive
// L = level = {cmos, ttl, schmitt} (default = cmos)
// P = pull-up resistor = {down, float, none, up}
// Vxx = {Vss, Vdd}
// subnet = connect supply to {pad, core, both}
asPadIn #(4,"1:4","","none") u1 (in, padIn);
asPadOut #(1,"5",13) u2 (padOut, d);
asPadTri #(1,"6",11) u3 (padTri, in[1], in[0]);
asPadBidir #(1,"7",2,"","") u4 (d, padBidir, in[3], in[2]);
asPadClk #(8) u5 (clk, padClk);
asPadOut #(1, "9") u6 (clkOut, clk);
asPadVdd #("10:11","pads") u7 (vddr);
asPadVss #("12,13","pads") u8 (vssr);
asPadVdd #("14","core") u9 (vddc);
asPadVss #("15","core") u10 (vssc);
asPadVdd #("16","both") u11 (vddb);
asPadVss #("17","both") u12 (vssb);
endmodule
<A NAME="anchor26486448"></A><HR ALIGN=LEFT>
module PadTri (Pad, I, Oen); // active-low output enable
parameter width = 1, pinNumbers = "", \strength = 1,
level = "CMOS", externalVdd = 5;
output [width-1:0] Pad; input [width-1:0] I; input Oen;
assign #1 Pad = (Oen ? {width{1'bz}} : I);
endmodule
<A NAME="anchor26486449"></A><HR ALIGN=LEFT>
module PadBidir (C, Pad, I, Oen); // active-low output enable
parameter width = 1, pinNumbers = "", \strength = 1,
level = "CMOS", pull = "none", externalVdd = 5;
output [width-1:0] C; inout [width-1:0] Pad;
input [width-1:0] I; input Oen;
assign #1 Pad = Oen ? {width{1'bz}} : I; assign #1 C = Pad;
endmodule
<A NAME="anchor26486450"></A><HR ALIGN=LEFT>
pc5o05 u2_2 (.PAD(padOut), .I(d));
pc5t04r u3_2 (.PAD(padTri), .I(in[1]), .OEN(in[0]));
pc5b01r u4_3 (.PAD(padBidir), .I(in[3]), .CIN(d), .OEN(in[2]));
pc5d01r u5_in_1 (.PAD(padClk), .CIN(u5toClkBuf[0]));
<A NAME="anchor26486451"></A><HR ALIGN=LEFT>
module dff(D,Q,Clock,Reset); // N.B. reset is active-low
output Q; input D,Clock,Reset;
parameter CARDINALITY = 1; reg [CARDINALITY-1:0] Q;
wire [CARDINALITY-1:0] D;
always @(posedge Clock) if (Reset!==0) #1 Q=D;
always begin wait (Reset==0); Q=0; wait (Reset==1); end
endmodule
<A NAME="anchor26486452"></A><HR ALIGN=LEFT>
module dff(D, Q, Clk, Rst); // new flip-flop for Viterbi decoder
parameter width = 1, reset_value = 0; input [width - 1 : 0] D;
output [width - 1 : 0] Q; reg [width - 1 : 0] Q; input Clk, Rst;
initial Q <= {width{1'bx}};
always @ ( posedge Clk or negedge Rst )
if ( Rst == 0 ) Q <= #1 reset_value; else Q <= #1 D;
endmodule
<A NAME="anchor26486453"></A><HR ALIGN=LEFT>/* This is the top-level module, viterbi_ASIC.v */
module viterbi_ASIC
(padin0, padin1, padin2, padin3, padin4, padin5, padin6, padin7,
padOut, padClk, padRes, padError);
input [2:0] padin0, padin1, padin2, padin3,
padin4, padin5, padin6, padin7;
input padRes, padClk; output padError; output [2:0] padOut;
wire Error, Clk, Res; wire [2:0] Out; // core
wire padError, padClk, padRes; wire [2:0] padOut;
wire [2:0] in0,in1,in2,in3,in4,in5,in6,in7; // core
wire [2:0]
padin0, padin1,padin2,padin3,padin4,padin5,padin6,padin7;
// Do not let the software mess with the pads.
//compass dontTouch u*
asPadIn #(3,"1,2,3") u0 (in0, padin0);
asPadIn #(3,"4,5,6") u1 (in1, padin1);
asPadIn #(3,"7,8,9") u2 (in2, padin2);
asPadIn #(3,"10,11,12") u3 (in3, padin3);
asPadIn #(3,"13,14,15") u4 (in4, padin4);
asPadIn #(3,"16,17,18") u5 (in5, padin5);
asPadIn #(3,"19,20,21") u6 (in6, padin6);
asPadIn #(3,"22,23,24") u7 (in7, padin7);
asPadVdd #("25","both") u25 (vddb);
asPadVss #("26","both") u26 (vssb);
asPadClk #("27") u27 (Clk, padClk);
asPadOut #(1,"28") u28 (padError, Error);
asPadin #(1,"29") u29 (Res, padRes);
asPadOut #(3,"30,31,32") u30 (padOut, Out);
// Here is the core module:
viterbi v_1
(in0,in1,in2,in3,in4,in5,in6,in7,Out,Clk,Res,Error);
endmodule
<A NAME="anchor26486454"></A><HR ALIGN=LEFT>module Step_Time(clk, phase);
input clk; output [2:0] phase; reg [2:0] phase;
always @(posedge clk) begin
phase <= 4'b0000;
phase <= #1 4'b0001; phase <= #2 4'b0010;
phase <= #3 4'b0011; phase <= #4 4'b0100;
end
endmodule
<A NAME="anchor26486455"></A><HR ALIGN=LEFT>
module Step_Count (clk_5x, phase);
input clk_5x; output [2:0] phase; reg [2:0] phase;
always@(posedge clk_5x)
case (phase)
0:phase = #1 1; 1:phase = #1 2; 2:phase = #1 3; 3:phase = #1 4;
default: phase = #1 0;
endcase
endmodule
<A NAME="anchor26486456"></A><HR ALIGN=LEFT>
module race(clk, q0); input clk, q0; reg q1, q2;
always @(posedge clk) q1 = #1 q0; always @(posedge clk) q2 = #1 q1;
endmodule
<A NAME="anchor26486457"></A><HR ALIGN=LEFT>
module no_race_1(clk, q0, q2); input clk, q0; output q2; reg q1, q2;
always @(posedge clk) begin q2 = q1; q1 = q0; end
endmodule
<A NAME="anchor26486458"></A><HR ALIGN=LEFT>
module no_race_2(clk, q0, q2); input clk, q0; output q2; reg q1, q2;
always @(posedge clk) q1 <= #1 q0; always @(posedge clk) q2 <= #1 q1;
endmodule
<A NAME="anchor26486459"></A><HR ALIGN=LEFT>
module And_Always(x, y, z); input x,y; output z; reg z;
always @(x or y) z <= x & y; // combinational logic method 1
endmodule
<A NAME="anchor26486460"></A><HR ALIGN=LEFT>
module And_Assign(x, y, z); input x,y; output z; wire z;
assign z <= x & y; // combinational logic method 2 = method 1
endmodule
<A NAME="anchor26486461"></A><HR ALIGN=LEFT>
module And_Or (a,b,c,z); input a,b,c; output z; reg [1:0]z;
always @(a or b or c) begin z[1]<= &{a,b,c}; z[2]<= |{a,b,c}; end
endmodule
<A NAME="anchor26486462"></A><HR ALIGN=LEFT>
module Parity (BusIn, outp); input[7:0] BusIn; output outp; reg outp;
always @(BusIn) if (^Busin == 0) outp = 1; else outp = 0;
endmodule
<A NAME="anchor26486463"></A><HR ALIGN=LEFT>
module And_Bad(a, b, c); input a, b; output c; reg c;
always@(a) c <= a & b; // b is missing from this sensitivity list
endmodule
<A NAME="anchor26486464"></A><HR ALIGN=LEFT>
module CL_good(a, b, c); input a, b; output c; reg c;
always@(a or b)
begin c = a + b; d = a & b; e = c + d; end // c, d: LHS before RHS
endmodule
module CL_bad(a, b, c); input a, b; output c; reg c;
always@(a or b)
begin e = c + d; c = a + b; d = a & b; end // c, d: RHS before LHS
endmodule
<A NAME="anchor26486465"></A><HR ALIGN=LEFT>
// The complement of this function is too big for synthesis.
module Achilles (out, in); output out; input [30:1] in;
assign out = in[30]&in[29]&in[28] | in[27]&in[26]&in[25]
| in[24]&in[23]&in[22] | in[21]&in[20]&in[19]
| in[18]&in[17]&in[16] | in[15]&in[14]&in[13]
| in[12]&in[11]&in[10] | in[9] & in[8]&in[7]
| in[6] & in[5]&in[4] | in[3] & in[2]&in[1];
endmodule
<A NAME="anchor26486466"></A><HR ALIGN=LEFT>
module Mux_21a(sel, a, b, z); input sel, a , b; output z; reg z;
always @(a or b or sel)
begin case(sel) 1'b0: z <= a; 1'b1: z <= b; end
endmodule
<A NAME="anchor26486467"></A><HR ALIGN=LEFT>
module Mux_x(sel, a, b, z); input sel, a, b; output z; reg z;
always @(a or b or sel)
begin case(sel) 1'b0: z <= 0; 1'b1: z <= 1; 1'bx: z <= 'x'; end
endmodule
<A NAME="anchor26486468"></A><HR ALIGN=LEFT>
module Mux_21b(sel, a, b, z); input sel, a, b; output z; reg z;
always @(a or b or sel) begin if (sel) z <= a else z <= b; end
endmodule
<A NAME="anchor26486469"></A><HR ALIGN=LEFT>
module Mux_Latch(sel, a, b, z); input sel, a, b; output z; reg z;
always @(a or sel) begin if (sel) z <= a; end
endmodule
<A NAME="anchor26486470"></A><HR ALIGN=LEFT>
module Mux_81(InBus, sel, OE, OutBit);
input [7:0] InBus; input [2:0] Sel;
input OE; output OutBit; reg OutBit;
always @(OE or sel or InBus)
begin
if (OE == 1) OutBit = InBus[sel]; else OutBit = 1'bz;
end
endmodule
<A NAME="anchor26486471"></A><HR ALIGN=LEFT>
module case8_oneHot(oneHot, a, b, c, z);
input a, b, c; input [2:0] oneHot; output z; reg z;
always @(oneHot or a or b or c)
begin case(oneHot) //synopsys full_case
3'b001: z <= a; 3'b010: z <= b; 3'b100: z <= c;
default: z <= 1'bx; endcase
end
endmodule
<A NAME="anchor26486472"></A><HR ALIGN=LEFT>
module case8_priority(oneHot, a, b, c, z);
input a, b, c; input [2:0] oneHot; output z; reg z;
always @(oneHot or a or b or c) begin
case(1'b1) //synopsys parallel_case
oneHot[0]: z <= a;
oneHot[1]: z <= b;
oneHot[2]: z <= c;
default: z <= 1'bx; endcase
end
endmodule
<A NAME="anchor26486473"></A><HR ALIGN=LEFT>
module Decoder_4To16(enable, In_4, Out_16); // 4-to-16 decoder
input enable; input [3:0] In_4; output [15:0] Out_16;
reg [15:0] Out_16;
always @(enable or In_4)
begin Out_16 = 16'hzzzz;
if (enable == 1)
begin Out_16 = 16'h0000; Out_16[In_4] = 1; end
end
endmodule
<A NAME="anchor26486474"></A><HR ALIGN=LEFT>
module Pri_Encoder32 (InBus, Clk, OE, OutBus);
input [31:0]InBus; input OE, Clk; output [4:0]OutBus;
reg j; reg [4:0]OutBus;
always@(posedge Clk)
begin
if (OE == 0) OutBus = 5'bz ;
else
begin OutBus = 0;
for (j = 31; j >= 0; j = j - 1)
begin if (InBus[j] == 1) OutBus = j; end
end
end
endmodule
<A NAME="anchor26486475"></A><HR ALIGN=LEFT>
module Adder_8 (A, B, Z, Cin, Cout);
input [7:0] A, B; input Cin; output [7:0] Z; output Cout;
assign {Cout, Z} = A + B + Cin;
endmodule
<A NAME="anchor26486476"></A><HR ALIGN=LEFT>
module Adder_16 (A, B, Sum, Cout);
input [15:0] A, B; output [15:0] Sum; output Cout;
reg [15:0] Sum; reg Cout;
always @(A or B) {Cout, Sum} = A + B + 1;
endmodule
<A NAME="anchor26486477"></A><HR ALIGN=LEFT>
module Add_A (sel, a, b, c, d, y);
input a, b, c, d, sel; output y; reg y;
always@(sel or a or b or c or d)
begin if (sel == 0) y <= a + b; else y <= c + d; end
endmodule
<A NAME="anchor26486478"></A><HR ALIGN=LEFT>
module Add_B (sel, a, b, c, d, y);
input a, b, c, d, sel; output y; reg t1, t2, y;
always@(sel or a or b or c or d) begin
if (sel == 0) begin t1 = a; t2 = b; end // Temporary
else begin t1 = c; t2 = d; end // variables.
y = t1 + t2; end
endmodule
<A NAME="anchor26486479"></A><HR ALIGN=LEFT>
module Multiply_unsigned (A, B, Z);
input [1:0] A, B; output [3:0] Z;
assign Z <= A * B;
endmodule
<A NAME="anchor26486480"></A><HR ALIGN=LEFT>
module Multiply_signed (A, B, Z);
input [1:0] A, B; output [3:0] Z;
// 00 -> 00_00 01 -> 00_01 10 -> 11_10 11 -> 11_11
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