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介绍asci设计的一本书

<P><dt><B>11 VERILOG HDL 479</B></P>

<P><dt>11.1 A Counter 480 <dt>11.2 Basics of the Verilog Language 482 <dd>11.2.1
Verilog Logic Values 483 <dd>11.2.2 Verilog Data Types 483 <dd>11.2.3 Other
Wire Types 486 <dd>11.2.4 Numbers 486 <dd>11.2.5 Negative Numbers 488 <dd>11.2.6
Strings 489 <dt>11.3 Operators 490 <dd>11.3.1 Arithmetic 492 <dt>11.4 Hierarchy
494 <dt>11.5 Procedures and Assignments 495 <dd>11.5.1 Continuous Assignment
Statement 496 <dd>11.5.2 Sequential Block 497 <dd>11.5.3 Procedural Assignments
498 <dt>11.6 Timing Controls and Delay 498 <dd>11.6.1 Timing Control 498
<dd>11.6.2 Data Slip 501 <dd>11.6.3 Wait Statement 502 <dd>11.6.4 Blocking
and Nonblocking Assignments 503 <dd>11.6.5 Procedural Continuous Assignment
504 <dt>11.7 Tasks and Functions 506 <dt>11.8 Control Statements 506 <dd>11.8.1
Case and If Statement 506 <dd>11.8.2 Loop Statement 507 <dd>11.8.3 Disable
508 <dd>11.8.4 Fork and Join 509 <dt>11.9 Logic-Gate Modeling 509 <dd>11.9.1
Built-in Logic Models 509 <dd>11.9.2 User-Defined Primitives 510 <dt>11.10
Modeling Delay 512 <dd>11.10.1 Net and Gate Delay 512 <dd>11.10.2 Pin-to-Pin
Delay 513 <dt>11.11 Altering Parameters 515 <dt>11.12 A Viterbi Decoder
515 <dd>11.12.1 Viterbi Encoder 515 <dd>11.12.2 The Received Signal 519
<dd>11.12.3 Testing the System 521 <dd>11.12.4 Verilog Decoder Model 523
<dt>11.13 Other Verilog Features 532 <dd>11.13.1 Display Tasks 533 <dd>11.13.2
File I/O Tasks 533 <dd>11.13.3 Timescale, Simulation, and Timing-Check Tasks
534 <dd>11.13.4 PLA Tasks 537 <dd>11.13.5 Stochastic Analysis Tasks 538
<dd>11.13.6 Simulation Time Functions 539 <dd>11.13.7 Conversion Functions
539 <dd>11.13.8 Probability Distribution Functions 540 <dd>11.13.9 Programming
Language Interface 541 <dt>11.14 Summary 541 <dt>11.15 Problems 543 <dd>11.15.1
The Viterbi Decoder 556 <dt>11.16 Bibliography 557 <dt>11.17 References
557</P>

<P><dt><B>12 LOGIC SYNTHESIS 559</B></P>

<P><dt>12.1 A Logic-Synthesis Example 560 <dt>12.2 A Comparator/MUX 561
<dd>12.2.1 An Actel Version of the Comparator/MUX 567 <dt>12.3 Inside a
Logic Synthesizer 569 <dt>12.4 Synthesis of the Viterbi Decoder 572 <dd>12.4.1
ASIC I/O 572 <dd>12.4.2 Flip-Flops 575 <dd>12.4.3 The Top-Level Model 575
<dt>12.5 Verilog and Logic Synthesis 580 <dd>12.5.1 Verilog Modeling 580
<dd>12.5.2 Delays in Verilog 581 <dd>12.5.3 Blocking and Nonblocking Assignments
582 <dd>12.5.4 Combinational Logic in Verilog 582 <dd>12.5.5 Multiplexers
In Verilog 584 <dd>12.5.6 The Verilog Case Statement 585 <dd>12.5.7 Decoders
In Verilog 586 <dd>12.5.8 Priority Encoder in Verilog 587 <dd>12.5.9 Arithmetic
in Verilog 587 <dd>12.5.10 Sequential Logic in Verilog 589 <dd>12.5.11 Component
Instantiation in Verilog 590 <dd>12.5.12 Datapath Synthesis in Verilog 591
<dt>12.6 VHDL and Logic Synthesis 593 <dd>12.6.1 Initialization and Reset
593 <dd>12.6.2 Combinational Logic Synthesis in VHDL 594 <dd>12.6.3 Multiplexers
in VHDL 594 <dd>12.6.4 Decoders in VHDL 595 <dd>12.6.5 Adders in VHDL 597
<dd>12.6.6 Sequential Logic in VHDL 597 <dd>12.6.7 Instantiation in VHDL
598 <dd>12.6.8 Shift Registers and Clocking in VHDL 601 <dd>12.6.9 Adders
and Arithmetic Functions 603 <dd>12.6.10 Adder/Subtracter and Don't Cares
604 <dt>12.7 Finite-State Machine Synthesis 605 <dd>12.7.1 FSM Synthesis
in Verilog 607 <dd>12.7.2 FSM Synthesis in VHDL 608 <dt>12.8 Memory Synthesis
611 <dd>12.8.1 Memory Synthesis in Verilog 611 <dd>12.8.2 Memory Synthesis
in VHDL 612 <dt>12.9 The Multiplier 614 <dd>12.9.1 Messages During Synthesis
617 <dt>12.10 The Engine Controller 619 <dt>12.11 Performance-Driven Synthesis
620 <dt>12.12 Optimization of the Viterbi Decoder 625 <dt>12.13 Summary
628 <dt>12.14 Problems 629 <dt>12.15 Bibliography 638 <dt>12.16 References
639</P>

<P><dt><B>13 SIMULATION 641</B></P>

<P><dt>13.1 Types of Simulation 641 <dt>13.2 The Comparator/MUX Example
643 <dd>13.2.1 Structural Simulation 644 <dd>13.2.2 Static Timing Analysis
647 <dd>13.2.3 Gate-Level Simulation 648 <dd>13.2.4 Net Capacitance 650
<dt>13.3 Logic Systems 652 <dd>13.3.1 Signal Resolution 653 <dd>13.3.2 Logic
Strength 653 <dt>13.4 How Logic Simulation Works 656 <dd>13.4.1 VHDL Simulation
Cycle 658 <dd>13.4.2 Delay 658 <dt>13.5 Cell Models 659 <dd>13.5.1 Primitive
Models 659 <dd>13.5.2 Synopsys Models 660 <dd>13.5.3 Verilog Models 661
<dd>13.5.4 VHDL Models 663 <dd>13.5.5 VITAL Models 664 <dd>13.5.6 SDF in
Simulation 667 <dt>13.6 Delay Models 669 <dd>13.6.1 Using a Library Data
Book 670 <dd>13.6.2 Input-Slope Delay Model 672 <dd>13.6.3 Limitations of
Logic Simulation 674 <dt>13.7 Static Timing Analysis 675 <dd>13.7.1 Hold
Time 678 <dd>13.7.2 Entry Delay 679 <dd>13.7.3 Exit Delay 680 <dd>13.7.4
External Setup Time 681 <dt>13.8 Formal Verification 682 <dd>13.8.1 An Example
682 <dd>13.8.2 Understanding Formal Verification 684 <dd>13.8.3 Adding an
Assertion 685 <dd>13.8.4 Completing a Proof 687 <dt>13.9 Switch-Level Simulation
688 <dt>13.10 Transistor-Level Simulation 689 <dd>13.10.1 A PSpice Example
689 <dd>13.10.2 SPICE Models 692 <dt>13.11 Summary 696 <dt>13.12 Problems
696 <dt>13.13 Bibliography 708 <dt>13.14 References 708</P>

<P><dt><B>14 TEST 711</B></P>

<P><dt>14.1 The Importance of Test 712 <dt>14.2 Boundary-Scan Test 714 <dd>14.2.1
BST Cells 716 <dd>14.2.2 BST Registers 718 <dd>14.2.3 Instruction Decoder
719 <dd>14.2.4 TAP Controller 722 <dd>14.2.5 Boundary-Scan Controller 724
<dd>14.2.6 A Simple Boundary-Scan Example 727 <dd>14.2.7 BSDL 732 <dt>14.3
Faults 736 <dd>14.3.1 Reliability 736 <dd>14.3.2 Fault Models 737 <dd>14.3.3
Physical Faults 738 <dd>14.3.4 Stuck-at Fault Model 740 <dd>14.3.5 Logical
Faults 741 <dd>14.3.6 IDDQ Test 742 <dd>14.3.7 Fault Collapsing 743 <dd>14.3.8
Fault-Collapsing Example 743 <dt>14.4 Fault Simulation 745 <dd>14.4.1 Serial
Fault Simulation 747 <dd>14.4.2 Parallel Fault Simulation 747 <dd>14.4.3
Concurrent Fault Simulation 747 <dd>14.4.4 Nondeterministic Fault Simulation
748 <dd>14.4.5 Fault-Simulation Results 748 <dd>14.4.6 Fault-Simulator Logic
Systems 749 <dd>14.4.7 Hardware Acceleration 751 <dd>14.4.8 A Fault-Simulation
Example 752 <dd>14.4.9 Fault Simulation in an ASIC Design Flow 754 <dt>14.5
Automatic Test-Pattern Generation 755 <dd>14.5.1 The D-Calculus 755 <dd>14.5.2
A Basic ATPG Algorithm 757 <dd>14.5.3 The PODEM Algorithm 759 <dd>14.5.4
Controllability and Observability 761 <dt>14.6 Scan Test 764 <dt>14.7 Built-in
Self-test 766 <dd>14.7.1 LFSR 766 <dd>14.7.2 Signature Analysis 766 <dd>14.7.3
A Simple BIST Example 767 <dd>14.7.4 Aliasing 768 <dd>14.7.5 LFSR Theory
771 <dd>14.7.6 LFSR Example 773 <dd>14.7.7 MISR 775 <dt>14.8 A Simple Test
Example 778 <dd>14.8.1 Test-Logic Insertion 778 <dd>14.8.2 How the Test
Software Works 780 <dd>14.8.3 ATVG and Fault Simulation 787 <dd>14.8.4 Test
Vectors 787 <dd>14.8.5 Production Tester Vector Formats 789 <dd>14.8.6 Test
Flow 791 <dt>14.9 The Viterbi Decoder Example 791 <dt>14.10 Summary 794
<dt>14.11 Problems 794 <dt>14.12 Bibliography 800 <dt>14.13 References 801</P>

<P><dt><B>15 ASIC CONSTRUCTION 805</B></P>

<P><dt>15.1 Physical Design 805 <dt>15.2 CAD Tools 807 <dd>15.2.1 Methods
and Algorithms 808 <dt>15.3 System Partitioning 809 <dt>15.4 Estimating
ASIC Size 811 <dt>15.5 Power Dissipation 816 <dd>15.5.1 Switching Current
816 <dd>15.5.2 Short-Circuit Current 817 <dd>15.5.3 Subthreshold and Leakage
Current 818 <dt>15.6 FPGA Partitioning 820 <dd>15.6.1 ATM Simulator 820
<dd>15.6.2 Automatic Partitioning with FPGAs 823 <dt>15.7 Partitioning Methods
824 <dd>15.7.1 Measuring Connectivity 824 <dd>15.7.2 A Simple Partitioning
Example 826 <dd>15.7.3 Constructive Partitioning 827 <dd>15.7.4 Iterative
Partitioning Improvement 828 <dd>15.7.5 The Kernighan-Lin Algorithm 829
<dd>15.7.6 The Ratio-Cut Algorithm 834 <dd>15.7.7 The Look-ahead Algorithm
835 <dd>15.7.8 Simulated Annealing 836 <dd>15.7.9 Other Partitioning Objectives
837 <dt>15.8 Summary 838 <dt>15.9 Problems 838 <dt>15.10 Bibliography 850
<dt>15.11 References 851</P>

<P><dt><B>16 FLOORPLANNING AND PLACEMENT 853</B></P>

<P><dt>16.1 Floorplanning 853 <dd>16.1.1 Floorplanning Goals and Objectives
854 <dd>16.1.2 Measurement of Delay inFloorplanning 856 <dd>16.1.3 Floorplanning
Tools 859 <dd>16.1.4 Channel Definition 861 <dd>16.1.5 I/O and Power Planning
864 <dd>16.1.6 Clock Planning 869 <dt>16.2 Placement 873 <dd>16.2.1 Placement
Terms and Definitions 873 <dd>16.2.2 Placement Goals and Objectives 876
<dd>16.2.3 Measurement of Placement Goals and Objectives 877 <dd>16.2.4
Placement Algorithms 882 <dd>16.2.5 Eigenvalue Placement Example 885 <dd>16.2.6
Iterative Placement Improvement 887 <dd>16.2.7 Placement Using Simulated
Annealing 890 <dd>16.2.8 Timing-Driven Placement Methods 891 <dd>16.2.9
A Simple Placement Example 893 <dt>16.3 Physical Design Flow 894 <dt>16.4
Information Formats 895 <dd>16.4.1 SDF for Floorplanning and Placement 895
<dd>16.4.2 PDEF 896 <dd>16.4.3 LEF and DEF 897 <dt>16.5 Summary 898 <dt>16.6
Problems 898 <dt>16.7 Bibliography 906 <dt>16.8 References 906</P>

<P><B><dt>17 ROUTING 909</B></P>

<P><dt>17.1 Global Routing 910 <dd>17.1.1 Goals and Objectives 911 <dd>17.1.2
Measurement of Interconnect Delay 912 <dd>17.1.3 Global Routing Methods
915 <dd>17.1.4 Global Routing Between Blocks 916 <dd>17.1.5 Global Routing
Inside Flexible Blocks 918 <dd>17.1.6 Timing-Driven Methods 920 <dd>17.1.7
Back-annotation 921 <dt>17.2 Detailed Routing 922 <dd>17.2.1 Goals and Objectives
926 <dd>17.2.2 Measurement of Channel Density 927 <dd>17.2.3 Algorithms
928 <dd>17.2.4 Left-Edge Algorithm 928 <dd>17.2.5 Constraints and Routing
Graphs 928 <dd>17.2.6 Area-Routing Algorithms 931 <dd>17.2.7 Multilevel
Routing 933 <dd>17.2.8 Timing-Driven Detailed Routing 933 <dd>17.2.9 Final
Routing Steps 934 <dt>17.3 Special Routing 935 <dd>17.3.1 Clock Routing
935 <dd>17.3.2 Power Routing 936 <dt>17.4 Circuit Extraction and DRC 939
<dd>17.4.1 SPF, RSPF, and DSPF 939 <dd>17.4.2 Design Checks 944 <dd>17.4.3
Mask Preparation 945 <dt>17.5 Summary 946 <dt>17.6 Problems 947 <dt>17.7
Bibliography 956 <dt>17.8 References 957</P>

<P><B><dt>A VHDL RESOURCES 961</B></P>

<P><dt>A.1 BNF 961 <dt>A.2 VHDL Syntax 963 <dt>A.3 BNF Index 973 <dt>A.4
Bibliography 973 <dt>A.5 References 976</P>

<P><B><dt>B VERILOG HDL RESOURCES 979</B></P>

<P><dt>B.1 Explanation of the Verilog HDL BNF 979 <dt>B.2 Verilog HDL Syntax
980 <dt>B.3 BNF Index 994 <dt>B.4 Verilog HDL LRM 994 <dt>B.5 Bibliography
997 <dt>B.6 References 999</P>

<P><B><dt>GLOSSARY 1000</B></P>

<P><B><dt>INDEX 1006</B>
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