gyk.v

基于FPGA的波束成型

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    10:09:05 06/02/07
// Design Name:    
// Module Name:    gyk
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

//W*Y(:,k)		在第四个CLK得到结果

module gyk(w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i,
		yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i,
		ykr,yki,clk,start,rdy);

input[15:0] w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i;
input[15:0] yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i;
input clk,start;

//output[31:0] z1i,z2i,z3i,z4i,z5i,z6i,z7i,z8i;
output[15:0] ykr,yki;
output rdy;

reg rdy=0;
wire rdy1,rdy2,rdy3,rdy4,rdy5,rdy6,rdy7,rdy8,rd1,rd2,rd3,rd4,rd5,rd6,rd7,rd8;

wire[31:0] z1r,z2r,z3r,z4r,z5r,z6r,z7r,z8r,z1i,z2i,z3i,z4i,z5i,z6i,z7i,z8i;
wire[15:0] q1r,q2r,q3r,q4r,q5r,q6r,q7r,q8r,q1i,q2i,q3i,q4i,q5i,q6i,q7i,q8i;
reg[15:0] ykr,yki;

	complexmul cm1(w0r,-w0i,yx0r,yx0i,z1r,z1i,clk,start,rdy1);
	complexmul cm2(w1r,-w1i,yx1r,yx1i,z2r,z2i,clk,start,rdy2);
	complexmul cm3(w2r,-w2i,yx2r,yx2i,z3r,z3i,clk,start,rdy3);
	complexmul cm4(w3r,-w3i,yx3r,yx3i,z4r,z4i,clk,start,rdy4);
	complexmul cm5(w4r,-w4i,yx4r,yx4i,z5r,z5i,clk,start,rdy5);
	complexmul cm6(w5r,-w5i,yx5r,yx5i,z6r,z6i,clk,start,rdy6);
	complexmul cm7(w6r,-w6i,yx6r,yx6i,z7r,z7i,clk,start,rdy7);
	complexmul cm8(w7r,-w7i,yx7r,yx7i,z8r,z8i,clk,start,rdy8);

	jiewei jyk1(z1r,z1i,q1r,q1i,clk,rdy1,rd1);
	jiewei jyk2(z2r,z2i,q2r,q2i,clk,rdy2,rd2);
	jiewei jyk3(z3r,z3i,q3r,q3i,clk,rdy3,rd3);
	jiewei jyk4(z4r,z4i,q4r,q4i,clk,rdy4,rd4);
	jiewei jyk5(z5r,z5i,q5r,q5i,clk,rdy5,rd5);
	jiewei jyk6(z6r,z6i,q6r,q6i,clk,rdy6,rd6);
	jiewei jyk7(z7r,z7i,q7r,q7i,clk,rdy7,rd7);
	jiewei jyk8(z8r,z8i,q8r,q8i,clk,rdy8,rd8);

	
	//assign ykr=z1r+z2r+z3r+z4r+z5r+z6r+z7r+z8r;
	//assign yki=z1i+z2i+z3i+z4i+z5i+z6i+z7i+z8i;
	
	always @ (posedge clk)
	begin
		if(rd1&&rd2&&rd3&&rd4&&rd5&&rd6&&rd7&&rd8)
			begin
				ykr<=q1r+q2r+q3r+q4r+q5r+q6r+q7r+q8r;
				yki<=q1i+q2i+q3i+q4i+q5i+q6i+q7i+q8i;
				rdy<=1;
			end
		else
			begin
				ykr<=16'b0;
				yki<=16'b0;
				rdy<=0;
			end
			
	end

endmodule