complexmul.syr

基于FPGA的波束成型

#      16-bit register             : 8
#      32-bit register             : 4
# Adders/Subtractors               : 14
#      16-bit adder                : 8
#      32-bit adder                : 5
#      32-bit subtractor           : 1
# Multipliers                      : 4
#      16x16-bit registered multiplier: 4

Cell Usage :
# BELS                             : 1267
#      GND                         : 1
#      INV                         : 245
#      LUT1                        : 8
#      LUT1_L                      : 4
#      LUT2                        : 138
#      LUT3                        : 113
#      LUT4                        : 20
#      LUT4_L                      : 124
#      MUXCY                       : 306
#      VCC                         : 1
#      XORCY                       : 307
# FlipFlops/Latches                : 253
#      FDE                         : 124
#      FDR                         : 129
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 130
#      IBUF                        : 65
#      OBUF                        : 65
# MULTs                            : 4
#      MULT18X18S                  : 4
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                     367  out of   3584    10%  
 Number of Slice Flip Flops:           253  out of   7168     3%  
 Number of 4 input LUTs:               407  out of   7168     5%  
 Number of bonded IOBs:                131  out of    141    92%  
 Number of MULT18X18s:                   4  out of     16    25%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 257   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.757ns (Maximum Frequency: 147.988MHz)
   Minimum input arrival time before clock: 6.181ns
   Maximum output required time after clock: 18.501ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 6.757ns (frequency: 147.988MHz)
  Total number of paths / destination ports: 2364 / 256
-------------------------------------------------------------------------
Delay:               6.757ns (Levels of Logic = 34)
  Source:            u4/Mmult__n00021_inst_mult_0 (MULT)
  Destination:       u4/out_31 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: u4/Mmult__n00021_inst_mult_0 to u4/out_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     MULT18X18S:C->P0      2   0.993   1.040  u4/Mmult__n00021_inst_mult_0 (u4/_n0003<0>)
     LUT1_L:I0->LO         1   0.479   0.000  u4/_n0003<0>_rt (u4/_n0003<0>_rt)
     MUXCY:S->O            1   0.435   0.000  u4/mult__n0006<0>cy (u4/mult__n0006<0>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<1>cy (u4/mult__n0006<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<2>cy (u4/mult__n0006<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<3>cy (u4/mult__n0006<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<4>cy (u4/mult__n0006<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<5>cy (u4/mult__n0006<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<6>cy (u4/mult__n0006<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<7>cy (u4/mult__n0006<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<8>cy (u4/mult__n0006<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<9>cy (u4/mult__n0006<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<10>cy (u4/mult__n0006<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<11>cy (u4/mult__n0006<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<12>cy (u4/mult__n0006<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<13>cy (u4/mult__n0006<13>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<14>cy (u4/mult__n0006<14>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<15>cy (u4/mult__n0006<15>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<16>cy (u4/mult__n0006<16>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<17>cy (u4/mult__n0006<17>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<18>cy (u4/mult__n0006<18>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<19>cy (u4/mult__n0006<19>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<20>cy (u4/mult__n0006<20>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<21>cy (u4/mult__n0006<21>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<22>cy (u4/mult__n0006<22>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<23>cy (u4/mult__n0006<23>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<24>cy (u4/mult__n0006<24>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<25>cy (u4/mult__n0006<25>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<26>cy (u4/mult__n0006<26>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<27>cy (u4/mult__n0006<27>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<28>cy (u4/mult__n0006<28>_cyo)
     MUXCY:CI->O           1   0.056   0.000  u4/mult__n0006<29>cy (u4/mult__n0006<29>_cyo)
     MUXCY:CI->O           0   0.056   0.000  u4/mult__n0006<30>cy (u4/mult__n0006<30>_cyo)
     XORCY:CI->O           1   0.786   0.704  u4/mult__n0006<31>_xor (u4/_n0006<31>)
     LUT4_L:I3->LO         1   0.479   0.000  u4/_n0003<31>1 (u4/_n0003<31>)
     FDR:D                     0.176          u4/out_31
    ----------------------------------------
    Total                      6.757ns (5.013ns logic, 1.744ns route)
                                       (74.2% logic, 25.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 1817 / 501
-------------------------------------------------------------------------
Offset:              6.181ns (Levels of Logic = 2)
  Source:            start (PAD)
  Destination:       u4/out_31 (FF)
  Destination Clock: clk rising

  Data Path: start to u4/out_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           129   0.715   2.047  start_IBUF (start_IBUF)
     INV:I->O            129   0.479   2.047  u4/out_N01_INV_0 (u4/out_N0)
     FDR:R                     0.892          u4/out_0
    ----------------------------------------
    Total                      6.181ns (2.086ns logic, 4.095ns route)
                                       (33.7% logic, 66.3% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 6336 / 65
-------------------------------------------------------------------------
Offset:              18.501ns (Levels of Logic = 39)
  Source:            u1/out_0 (FF)
  Destination:       rdy (PAD)
  Source Clock:      clk rising

  Data Path: u1/out_0 to rdy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.626   0.976  u1/out_0 (u1/out_0)
     LUT2:I0->O            1   0.479   0.000  complexmul__n0000<0>lut (N36)
     MUXCY:S->O            1   0.435   0.000  complexmul__n0000<0>cy (complexmul__n0000<0>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<1>cy (complexmul__n0000<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<2>cy (complexmul__n0000<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<3>cy (complexmul__n0000<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<4>cy (complexmul__n0000<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<5>cy (complexmul__n0000<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<6>cy (complexmul__n0000<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<7>cy (complexmul__n0000<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<8>cy (complexmul__n0000<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<9>cy (complexmul__n0000<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<10>cy (complexmul__n0000<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<11>cy (complexmul__n0000<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<12>cy (complexmul__n0000<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<13>cy (complexmul__n0000<13>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<14>cy (complexmul__n0000<14>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<15>cy (complexmul__n0000<15>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<16>cy (complexmul__n0000<16>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<17>cy (complexmul__n0000<17>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<18>cy (complexmul__n0000<18>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<19>cy (complexmul__n0000<19>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<20>cy (complexmul__n0000<20>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<21>cy (complexmul__n0000<21>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<22>cy (complexmul__n0000<22>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<23>cy (complexmul__n0000<23>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<24>cy (complexmul__n0000<24>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<25>cy (complexmul__n0000<25>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<26>cy (complexmul__n0000<26>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<27>cy (complexmul__n0000<27>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<28>cy (complexmul__n0000<28>_cyo)
     MUXCY:CI->O           1   0.056   0.000  complexmul__n0000<29>cy (complexmul__n0000<29>_cyo)
     XORCY:CI->O           1   0.786   0.851  complexmul__n0000<30>_xor (_n0000<30>)
     LUT2:I1->O            2   0.479   1.040  qr<30>1 (qr_30_OBUF)
     LUT4:I0->O            1   0.479   0.851  _n000371 (CHOICE410)
     LUT4:I1->O            1   0.479   0.704  _n000380_SW0 (N208)
     LUT4:I3->O            1   0.479   0.704  _n000380 (CHOICE412)
     LUT4:I3->O            1   0.479   0.976  _n000392 (CHOICE413)
     LUT2:I0->O            1   0.479   0.681  _n0003202 (rdy_OBUF)
     OBUF:I->O                 4.909          rdy_OBUF (rdy)
    ----------------------------------------
    Total                     18.501ns (11.719ns logic, 6.782ns route)
                                       (63.3% logic, 36.7% route)

=========================================================================
CPU : 19.22 / 23.06 s | Elapsed : 20.00 / 22.00 s
 
--> 

Total memory usage is 103848 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    7 (   0 filtered)
Number of infos    :    0 (   0 filtered)