eexywave.tbw

基于FPGA的波束成型

version 3
f:\myfpga\xilinx\wopt\eexy.v
eexy
VERILOG
VERILOG
eexywave.xwv
Clocked
-
-
10000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clk
100000000
100000000
15000000
15000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
eei
clk
eer
clk
rdy
clk
start
clk
tey0i
clk
tey0r
clk
tey1i
clk
tey1r
clk
tey2i
clk
tey2r
clk
tey3i
clk
tey3r
clk
tey4i
clk
tey4r
clk
tey5i
clk
tey5r
clk
tey6i
clk
tey6r
clk
tey7i
clk
tey7r
clk
yx0i
clk
yx0r
clk
yx1i
clk
yx1r
clk
yx2i
clk
yx2r
clk
yx3i
clk
yx3r
clk
yx4i
clk
yx4r
clk
yx5i
clk
yx5r
clk
yx6i
clk
yx6r
clk
yx7i
clk
yx7r
clk
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
rdy_DIFF
tey0i_DIFF
tey0r_DIFF
tey1i_DIFF
tey1r_DIFF
tey2i_DIFF
tey2r_DIFF
tey3i_DIFF
tey3r_DIFF
tey4i_DIFF
tey4r_DIFF
tey5i_DIFF
tey5r_DIFF
tey6i_DIFF
tey6r_DIFF
tey7i_DIFF
tey7r_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clk
start
rdy
eei
eer
yx0i
yx0r
yx1i
yx1r
yx2i
yx2r
yx3i
yx3r
yx4i
yx4r
yx5i
yx5r
yx6i
yx6r
yx7i
yx7r
tey0i
tey0r
tey1i
tey1r
tey2i
tey2r
tey3i
tey3r
tey4i
tey4r
tey5i
tey5r
tey6i
tey6r
tey7i
tey7r
SIGNAL_ORDER_END
-X-X-X-