gw.v

基于FPGA的波束成型

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    10:52:06 06/02/07
// Design Name:    
// Module Name:    gw
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module gw(mux2,eer,eei,
			w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i,
			yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i,
			wn0r,wn0i,wn1r,wn1i,wn2r,wn2i,wn3r,wn3i,wn4r,wn4i,wn5r,wn5i,wn6r,wn6i,wn7r,wn7i,
			clk,start,rdy);

input[15:0] mux2,eer,eei;
input[15:0] w0r,w0i,w1r,w1i,w2r,w2i,w3r,w3i,w4r,w4i,w5r,w5i,w6r,w6i,w7r,w7i;
input[15:0] yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i;
input clk,start;

output[15:0] wn0r,wn0i,wn1r,wn1i,wn2r,wn2i,wn3r,wn3i,wn4r,wn4i,wn5r,wn5i,wn6r,wn6i,wn7r,wn7i;
output rdy;

reg rdy=0;
reg[15:0] wn0r,wn0i,wn1r,wn1i,wn2r,wn2i,wn3r,wn3i,wn4r,wn4i,wn5r,wn5i,wn6r,wn6i,wn7r,wn7i;

wire[15:0] temp0r,temp0i,temp1r,temp1i,temp2r,temp2i,temp3r,temp3i,temp4r,temp4i,temp5r,temp5i,temp6r,temp6i,temp7r,temp7i;

wire rdy1,rdy2;
wire[31:0] qr,qi;


muxe mue1(mux2,eer,eei,qr,qi,clk,start,rdy1);//32位输出

eexy eey1(qr,qi,yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i,
				temp0r,temp0i,temp1r,temp1i,temp2r,temp2i,temp3r,temp3i,temp4r,temp4i,temp5r,temp5i,temp6r,temp6i,temp7r,temp7i,
				clk,rdy1,rdy2);



always @ (posedge clk)
	begin
		if(start&&rdy2)
			begin
				wn0r<=w0r+temp0r;
				wn1r<=w1r+temp1r;
				wn2r<=w2r+temp2r;
				wn3r<=w3r+temp3r;
				wn4r<=w4r+temp4r;
				wn5r<=w5r+temp5r;
				wn6r<=w6r+temp6r;
				wn7r<=w7r+temp7r;

				wn0i<=w0i+temp0i;
				wn1i<=w1i+temp1i;
				wn2i<=w2i+temp2i;
				wn3i<=w3i+temp3i;
				wn4i<=w4i+temp4i;
				wn5i<=w5i+temp5i;
				wn6i<=w6i+temp6i;
				wn7i<=w7i+temp7i;

				rdy<=1;

			end
		else
			begin
				wn0r<=16'b0;
				wn1r<=16'b0;
				wn2r<=16'b0;
				wn3r<=16'b0;
				wn4r<=16'b0;
				wn5r<=16'b0;
				wn6r<=16'b0;
				wn7r<=16'b0;

				wn0i<=16'b0;
				wn1i<=16'b0;
				wn2i<=16'b0;
				wn3i<=16'b0;
				wn4i<=16'b0;
				wn5i<=16'b0;
				wn6i<=16'b0;
				wn7i<=16'b0;

				rdy<=0;


			end
	end


	
endmodule