muxe.syr

基于FPGA的波束成型

# Registers                        : 152
#      1-bit register              : 40
#      16-bit register             : 80
#      32-bit register             : 32
# Adders/Subtractors               : 112
#      16-bit adder                : 64
#      32-bit adder                : 40
#      32-bit subtractor           : 8
# Multipliers                      : 32
#      16x16-bit registered multiplier: 32

Cell Usage :
# BELS                             : 8978
#      BUF                         : 2
#      GND                         : 1
#      INV                         : 1715
#      LUT1                        : 80
#      LUT2                        : 305
#      LUT2_L                      : 520
#      LUT3                        : 712
#      LUT3_L                      : 32
#      LUT4                        : 1138
#      LUT4_D                      : 8
#      LUT4_L                      : 40
#      MUXCY                       : 2208
#      VCC                         : 1
#      XORCY                       : 2216
# FlipFlops/Latches                : 2028
#      FDE                         : 737
#      FDR                         : 1291
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 530
#      IBUF                        : 273
#      OBUF                        : 257
# MULTs                            : 32
#      MULT18X18S                  : 32
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                    2532  out of   3584    70%  
 Number of Slice Flip Flops:          2028  out of   7168    28%  
 Number of 4 input LUTs:              2835  out of   7168    39%  
 Number of bonded IOBs:                531  out of    141   376% (*) 
 Number of MULT18X18s:                  32  out of     16   200% (*) 
 Number of GCLKs:                        1  out of      8    12%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 2060  |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 11.287ns (Maximum Frequency: 88.601MHz)
   Minimum input arrival time before clock: 12.257ns
   Maximum output required time after clock: 9.126ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 11.287ns (frequency: 88.601MHz)
  Total number of paths / destination ports: 857072 / 2312
-------------------------------------------------------------------------
Delay:               11.287ns (Levels of Logic = 35)
  Source:            mw8/u3/out_0 (FF)
  Destination:       jmu8/rdy (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: mw8/u3/out_0 to jmu8/rdy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.626   1.040  mw8/u3/out_0 (mw8/u3/out_0)
     LUT2_L:I0->LO         1   0.479   0.000  mw8/complexmul__n0001<0>lut (mw8/N4)
     MUXCY:S->O            1   0.435   0.000  mw8/complexmul__n0001<0>cy (mw8/complexmul__n0001<0>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<1>cy (mw8/complexmul__n0001<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<2>cy (mw8/complexmul__n0001<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<3>cy (mw8/complexmul__n0001<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<4>cy (mw8/complexmul__n0001<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<5>cy (mw8/complexmul__n0001<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<6>cy (mw8/complexmul__n0001<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<7>cy (mw8/complexmul__n0001<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<8>cy (mw8/complexmul__n0001<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<9>cy (mw8/complexmul__n0001<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<10>cy (mw8/complexmul__n0001<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<11>cy (mw8/complexmul__n0001<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<12>cy (mw8/complexmul__n0001<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<13>cy (mw8/complexmul__n0001<13>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<14>cy (mw8/complexmul__n0001<14>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<15>cy (mw8/complexmul__n0001<15>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<16>cy (mw8/complexmul__n0001<16>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<17>cy (mw8/complexmul__n0001<17>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<18>cy (mw8/complexmul__n0001<18>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<19>cy (mw8/complexmul__n0001<19>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<20>cy (mw8/complexmul__n0001<20>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<21>cy (mw8/complexmul__n0001<21>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<22>cy (mw8/complexmul__n0001<22>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<23>cy (mw8/complexmul__n0001<23>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<24>cy (mw8/complexmul__n0001<24>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<25>cy (mw8/complexmul__n0001<25>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<26>cy (mw8/complexmul__n0001<26>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<27>cy (mw8/complexmul__n0001<27>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<28>cy (mw8/complexmul__n0001<28>_cyo)
     MUXCY:CI->O           1   0.056   0.000  mw8/complexmul__n0001<29>cy (mw8/complexmul__n0001<29>_cyo)
     XORCY:CI->O           1   0.786   0.976  mw8/complexmul__n0001<30>_xor (mw8/_n0001<30>)
     LUT4:I0->O            1   0.479   0.976  mw8/_n0003286 (CHOICE476)
     LUT4:I0->O            4   0.479   1.074  mw8/_n0003366 (CHOICE496)
     LUT4:I0->O            9   0.479   0.955  jmu8/rdy_N01_3 (jmu8/rdy_N012)
     FDR:R                     0.892          jmu8/qr_2
    ----------------------------------------
    Total                     11.287ns (6.265ns logic, 5.022ns route)
                                       (55.5% logic, 44.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 11141 / 3493
-------------------------------------------------------------------------
Offset:              12.257ns (Levels of Logic = 3)
  Source:            start (PAD)
  Destination:       mw1/u4/out_31 (FF)
  Destination Clock: clk rising

  Data Path: start to mw1/u4/out_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           386   0.715   3.299  start_IBUF (start_IBUF)
     BUF:I->O            387   0.479   3.304  start_IBUF_1 (start_IBUF_1)
     INV:I->O            343   0.479   3.089  mw8/u4/rdy_N01_INV_0 (mw8/u4/rdy_N0)
     FDR:R                     0.892          mw3/u2/out_7
    ----------------------------------------
    Total                     12.257ns (2.565ns logic, 9.692ns route)
                                       (20.9% logic, 79.1% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 264 / 257
-------------------------------------------------------------------------
Offset:              9.126ns (Levels of Logic = 3)
  Source:            jmu1/rdy (FF)
  Destination:       rdy (PAD)
  Source Clock:      clk rising

  Data Path: jmu1/rdy to rdy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.626   0.976  jmu1/rdy (jmu1/rdy)
     LUT4:I0->O            1   0.479   0.976  rdy4 (CHOICE399)
     LUT2:I0->O            1   0.479   0.681  rdy10 (rdy_OBUF)
     OBUF:I->O                 4.909          rdy_OBUF (rdy)
    ----------------------------------------
    Total                      9.126ns (6.493ns logic, 2.633ns route)
                                       (71.2% logic, 28.8% route)

=========================================================================
CPU : 98.80 / 99.64 s | Elapsed : 98.00 / 99.00 s
 
--> 

Total memory usage is 131332 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  288 (   0 filtered)
Number of infos    :    0 (   0 filtered)