muxe.syr

基于FPGA的波束成型

Release 7.1.03i - xst H.41
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.78 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.78 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: muxe.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "muxe.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "muxe"
Output Format                      : NGC
Target Device                      : xc3s400-5-pq208

---- Source Options
Top Module Name                    : muxe
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : muxe.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "../complexmul.v"
Module <complexmul> compiled
Module <mult> compiled
Compiling verilog file "../cutbit/jiewei.v"
Module <jiewei> compiled
Compiling verilog file "muxe.v"
Module <muxe> compiled
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 
No errors in compilation
Analysis of file <"muxe.prj"> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
WARNING:HDLCompilers:259 - "muxe.v" line 32 Connection to input port 'ai' does not match port size
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:259 - "muxe.v" line 33 Connection to input port 'ai' does not match port size
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:259 - "muxe.v" line 34 Connection to input port 'ai' does not match port size
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:259 - "muxe.v" line 35 Connection to input port 'ai' does not match port size
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:259 - "muxe.v" line 36 Connection to input port 'ai' does not match port size
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:259 - "muxe.v" line 37 Connection to input port 'ai' does not match port size
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:259 - "muxe.v" line 38 Connection to input port 'ai' does not match port size
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:259 - "muxe.v" line 39 Connection to input port 'ai' does not match port size
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qr' overrides range on output declaration at "../complexmul.v" line 11 
WARNING:HDLCompilers:258 - "../complexmul.v" line 15 Range on redeclaration of 'qi' overrides range on output declaration at "../complexmul.v" line 11 
Analyzing top module <muxe>.
Module <muxe> is correct for synthesis.
 
Analyzing module <complexmul>.
WARNING:Xst:905 - "../complexmul.v" line 32: The signals <rdy1, rdy2, rdy3, rdy4> are missing in the sensitivity list of always block.
Module <complexmul> is correct for synthesis.
 
Analyzing module <mult>.
WARNING:Xst:854 - "../complexmul.v" line 78: Ignored initial statement.
Module <mult> is correct for synthesis.
 
Analyzing module <jiewei>.
Module <jiewei> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mult>.
    Related source file is "../complexmul.v".
WARNING:Xst:1780 - Signal <dj> is never used or assigned.
    Found 1-bit register for signal <rdy>.
    Found 32-bit register for signal <out>.
    Found 16x16-bit multiplier for signal <$n0002> created at line 105.
    Found 16-bit adder for signal <$n0004> created at line 94.
    Found 16-bit adder for signal <$n0005> created at line 100.
    Found 32-bit adder for signal <$n0006> created at line 109.
    Found 16-bit register for signal <ain>.
    Found 16-bit register for signal <bin>.
    Found 32-bit register for signal <outab>.
    Found 1-bit xor2 for signal <tk>.
    Summary:
	inferred  97 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
Unit <mult> synthesized.


Synthesizing Unit <jiewei>.
    Related source file is "../cutbit/jiewei.v".
WARNING:Xst:647 - Input <ai<9:0>> is never used.
WARNING:Xst:647 - Input <ar<9:0>> is never used.
    Found 16-bit register for signal <qi>.
    Found 16-bit register for signal <qr>.
    Found 1-bit register for signal <rdy>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <jiewei> synthesized.


Synthesizing Unit <complexmul>.
    Related source file is "../complexmul.v".
    Found 32-bit subtractor for signal <$n0000> created at line 35.
    Found 32-bit adder for signal <$n0001> created at line 36.
    Summary:
	inferred   2 Adder/Subtractor(s).
Unit <complexmul> synthesized.