eexywave.fdo

来自「基于FPGA的波束成型」· FDO 代码 · 共 17 行

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Sat Jun 02 12:32:48 涓?鍥芥爣鍑嗘椂闂? 2007
##
vlib work
vlog  ../complexmul.v
vlog  ../cutbit/jiewei.v
vlog  eexy.v
vlog  eexywave.tfw
vlog  "D:/Xilinx/verilog/src/glbl.v"
vsim -t 1ps  -L xilinxcorelib_ver -L unisims_ver  -lib work eexywave glbl
do {eexywave.udo}
view wave
add wave *
view structure
view signals
run -all