eexy.v

基于FPGA的波束成型

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    11:45:16 06/02/07
// Design Name:    
// Module Name:    eexy
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//4个CLK
// 
////////////////////////////////////////////////////////////////////////////////
module eexy(mer,mei,yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i,
				tey0r,tey0i,tey1r,tey1i,tey2r,tey2i,tey3r,tey3i,tey4r,tey4i,tey5r,tey5i,tey6r,tey6i,tey7r,tey7i,
				clk,start,rdy);

input[15:0] yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i;
input[31:0] mer,mei;
input clk,start;
output[15:0] tey0r,tey0i,tey1r,tey1i,tey2r,tey2i,tey3r,tey3i,tey4r,tey4i,tey5r,tey5i,tey6r,tey6i,tey7r,tey7i;
output rdy;
wire rdy1,rdy2,rdy3,rdy4,rdy5,rdy6,rdy7,rdy8,rd1,rd2,rd3,rd4,rd5,rd6,rd7,rd8,rdyzh;
wire[63:0] q0r,q0i,q1r,q1i,q2r,q2i,q3r,q3i,q4r,q4i,q5r,q5i,q6r,q6i,q7r,q7i;
wire[31:0] z0r,z0i,z1r,z1i,z2r,z2i,z3r,z3i,z4r,z4i,z5r,z5i,z6r,z6i,z7r,z7i;

/*																					 
assign tp0r=yx0r;
assign tp1r=yx1r;
assign tp2r=yx2r;
assign tp3r=yx3r;
assign tp4r=yx4r;
assign tp5r=yx5r;
assign tp6r=yx6r;
assign tp7r=yx7r;

assign tp0i=yx0i;
assign tp1i=yx1i;
assign tp2i=yx2i;
assign tp3i=yx3i;
assign tp4i=yx4i;
assign tp5i=yx5i;
assign tp6i=yx6i;
assign tp7i=yx7i;
*/
zh32 zhuanhuan(yx0r,yx0i,yx1r,yx1i,yx2r,yx2i,yx3r,yx3i,yx4r,yx4i,yx5r,yx5i,yx6r,yx6i,yx7r,yx7i,
				z0r,z0i,z1r,z1i,z2r,z2i,z3r,z3i,z4r,z4i,z5r,z5i,z6r,z6i,z7r,z7i,clk,start,rdyzh);

cmpmul32 muw1(mer,-mei,z0r,z0i,q0r,q0i,clk,rdyzh,rdy1);
cmpmul32 muw2(mer,-mei,z1r,z1i,q1r,q1i,clk,rdyzh,rdy2);
cmpmul32 muw3(mer,-mei,z2r,z2i,q2r,q2i,clk,rdyzh,rdy3);
cmpmul32 muw4(mer,-mei,z3r,z3i,q3r,q3i,clk,rdyzh,rdy4);
cmpmul32 muw5(mer,-mei,z4r,z4i,q4r,q4i,clk,rdyzh,rdy5);
cmpmul32 muw6(mer,-mei,z5r,z5i,q5r,q5i,clk,rdyzh,rdy6);
cmpmul32 muw7(mer,-mei,z6r,z6i,q6r,q6i,clk,rdyzh,rdy7);
cmpmul32 muw8(mer,-mei,z7r,z7i,q7r,q7i,clk,rdyzh,rdy8);

/*
cmpmul32 mulw1(eer,eei,yx0r,yx0i,q0r,q0i,clk,start,rdy1);
cmpmul32 mulw2(eer,eei,yx1r,yx1i,q1r,q1i,clk,start,rdy2);
cmpmul32 mulw3(eer,eei,yx2r,yx2i,q2r,q2i,clk,start,rdy3);
cmpmul32 mulw4(eer,eei,yx3r,yx3i,q3r,q3i,clk,start,rdy4);
cmpmul32 mulw5(eer,eei,yx4r,yx4i,q4r,q4i,clk,start,rdy5);
cmpmul32 mulw6(eer,eei,yx5r,yx5i,q5r,q5i,clk,start,rdy6);
cmpmul32 mulw7(eer,eei,yx6r,yx6i,q6r,q6i,clk,start,rdy7);
cmpmul32 mulw8(eer,eei,yx7r,yx7i,q7r,q7i,clk,start,rdy8);
*/

jiewei2 jw1(q0r,q0i,tey0r,tey0i,clk,rdy1,rd1);
jiewei2 jw2(q1r,q1i,tey1r,tey1i,clk,rdy2,rd2);
jiewei2 jw3(q2r,q2i,tey2r,tey2i,clk,rdy3,rd3);
jiewei2 jw4(q3r,q3i,tey3r,tey3i,clk,rdy4,rd4);
jiewei2 jw5(q4r,q4i,tey4r,tey4i,clk,rdy5,rd5);
jiewei2 jw6(q5r,q5i,tey5r,tey5i,clk,rdy6,rd6);
jiewei2 jw7(q6r,q6i,tey6r,tey6i,clk,rdy7,rd7);
jiewei2 jw8(q7r,q7i,tey7r,tey7i,clk,rdy8,rd8);

assign rdy=rd1&&rd2&&rd3&&rd4&&rd5&&rd6&&rd7&&rd8;



endmodule