_primary.vhd

基于FPGA的波束成型

library verilog;
use verilog.vl_types.all;
entity eexy is
    port(
        eer             : in     vl_logic_vector(15 downto 0);
        eei             : in     vl_logic_vector(15 downto 0);
        yx0r            : in     vl_logic_vector(15 downto 0);
        yx0i            : in     vl_logic_vector(15 downto 0);
        yx1r            : in     vl_logic_vector(15 downto 0);
        yx1i            : in     vl_logic_vector(15 downto 0);
        yx2r            : in     vl_logic_vector(15 downto 0);
        yx2i            : in     vl_logic_vector(15 downto 0);
        yx3r            : in     vl_logic_vector(15 downto 0);
        yx3i            : in     vl_logic_vector(15 downto 0);
        yx4r            : in     vl_logic_vector(15 downto 0);
        yx4i            : in     vl_logic_vector(15 downto 0);
        yx5r            : in     vl_logic_vector(15 downto 0);
        yx5i            : in     vl_logic_vector(15 downto 0);
        yx6r            : in     vl_logic_vector(15 downto 0);
        yx6i            : in     vl_logic_vector(15 downto 0);
        yx7r            : in     vl_logic_vector(15 downto 0);
        yx7i            : in     vl_logic_vector(15 downto 0);
        tey0r           : out    vl_logic_vector(15 downto 0);
        tey0i           : out    vl_logic_vector(15 downto 0);
        tey1r           : out    vl_logic_vector(15 downto 0);
        tey1i           : out    vl_logic_vector(15 downto 0);
        tey2r           : out    vl_logic_vector(15 downto 0);
        tey2i           : out    vl_logic_vector(15 downto 0);
        tey3r           : out    vl_logic_vector(15 downto 0);
        tey3i           : out    vl_logic_vector(15 downto 0);
        tey4r           : out    vl_logic_vector(15 downto 0);
        tey4i           : out    vl_logic_vector(15 downto 0);
        tey5r           : out    vl_logic_vector(15 downto 0);
        tey5i           : out    vl_logic_vector(15 downto 0);
        tey6r           : out    vl_logic_vector(15 downto 0);
        tey6i           : out    vl_logic_vector(15 downto 0);
        tey7r           : out    vl_logic_vector(15 downto 0);
        tey7i           : out    vl_logic_vector(15 downto 0);
        clk             : in     vl_logic;
        start           : in     vl_logic;
        rdy             : out    vl_logic
    );
end eexy;