gw.syr

来自「基于FPGA的波束成型」· SYR 代码 · 共 856 行 · 第 1/5 页

Register <eey1/mulw2/u2/bin_0> equivalent to <eey1/mulw2/u3/bin_0> has been removed
Register <eey1/mulw1/u1/bin_0> equivalent to <eey1/mulw1/u4/bin_0> has been removed
Register <eey1/mulw1/u2/bin_0> equivalent to <eey1/mulw1/u3/bin_0> has been removed
Register <mue1/mw8/u1/bin_0> equivalent to <mue1/mw8/u4/bin_0> has been removed
Register <mue1/mw2/u3/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw4/u3/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw6/u3/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw3/u3/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw8/u1/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw7/u3/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw7/u1/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw4/u1/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw6/u1/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw3/u1/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw5/u3/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw5/u1/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
Register <mue1/mw8/u2/bin_0> equivalent to <mue1/mw8/u3/bin_0> has been removed
Register <mue1/mw7/u1/bin_0> equivalent to <mue1/mw7/u4/bin_0> has been removed
Register <mue1/mw7/u2/bin_0> equivalent to <mue1/mw7/u3/bin_0> has been removed
Register <mue1/mw6/u1/bin_0> equivalent to <mue1/mw6/u4/bin_0> has been removed
Register <mue1/mw6/u2/bin_0> equivalent to <mue1/mw6/u3/bin_0> has been removed
Register <mue1/mw1/u1/bin_0> equivalent to <mue1/mw1/u4/bin_0> has been removed
Register <mue1/mw5/u1/bin_0> equivalent to <mue1/mw5/u4/bin_0> has been removed
Register <mue1/mw5/u2/bin_0> equivalent to <mue1/mw5/u3/bin_0> has been removed
Register <mue1/mw4/u1/bin_0> equivalent to <mue1/mw4/u4/bin_0> has been removed
Register <mue1/mw4/u2/bin_0> equivalent to <mue1/mw4/u3/bin_0> has been removed
Register <mue1/mw1/u1/ain_0> equivalent to <mue1/mw2/u1/ain_0> has been removed
Register <mue1/mw1/u3/ain_0> equivalent to <mue1/mw2/u1/ain_0> has been removed
Register <mue1/mw1/u2/bin_0> equivalent to <mue1/mw1/u3/bin_0> has been removed
Register <mue1/mw3/u1/bin_0> equivalent to <mue1/mw3/u4/bin_0> has been removed
Register <mue1/mw3/u2/bin_0> equivalent to <mue1/mw3/u3/bin_0> has been removed
Register <mue1/mw2/u1/bin_0> equivalent to <mue1/mw2/u4/bin_0> has been removed
Register <mue1/mw2/u2/bin_0> equivalent to <mue1/mw2/u3/bin_0> has been removed
Register <mue1/mw2/u1/ain_0> equivalent to <mue1/mw8/u3/ain_0> has been removed
FlipFlop eey1/mulw8/u4/rdy has been replicated 2 time(s)
FlipFlop mue1/mw8/u4/rdy has been replicated 2 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : gw.ngr
Top Level Output File Name         : gw
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 819

Macro Statistics :
# Registers                        : 321
#      1-bit register              : 81
#      16-bit register             : 176
#      32-bit register             : 64
# Adders/Subtractors               : 241
#      16-bit adder                : 145
#      32-bit adder                : 80
#      32-bit subtractor           : 16
# Multipliers                      : 64
#      16x16-bit registered multiplier: 64

Cell Usage :
# BELS                             : 19699
#      BUF                         : 5
#      GND                         : 1
#      INV                         : 3682
#      LUT1                        : 177
#      LUT2                        : 791
#      LUT2_D                      : 80
#      LUT2_L                      : 1056
#      LUT3                        : 1664
#      LUT3_L                      : 16
#      LUT4                        : 2289
#      LUT4_D                      : 18
#      LUT4_L                      : 81
#      MUXCY                       : 4911
#      VCC                         : 1
#      XORCY                       : 4927
# FlipFlops/Latches                : 4554
#      FDE                         : 1715
#      FDR                         : 2839
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 818
#      IBUF                        : 561
#      OBUF                        : 257
# MULTs                            : 64
#      MULT18X18S                  : 64
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                    5485  out of   3584   153% (*) 
 Number of Slice Flip Flops:          4554  out of   7168    63%  
 Number of 4 input LUTs:              6172  out of   7168    86%  
 Number of bonded IOBs:                819  out of    141   580% (*) 
 Number of MULT18X18s:                  64  out of     16   400% (*) 
 Number of GCLKs:                        1  out of      8    12%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 4618  |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 11.162ns (Maximum Frequency: 89.594MHz)
   Minimum input arrival time before clock: 14.326ns
   Maximum output required time after clock: 6.216ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 11.162ns (frequency: 89.594MHz)
  Total number of paths / destination ports: 1741640 / 7653
-------------------------------------------------------------------------
Delay:               11.162ns (Levels of Logic = 35)
  Source:            eey1/mulw8/u3/out_0 (FF)
  Destination:       eey1/jw8/rdy (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: eey1/mulw8/u3/out_0 to eey1/jw8/rdy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   0.626   1.040  eey1/mulw8/u3/out_0 (eey1/mulw8/u3/out_0)
     LUT2_L:I0->LO         1   0.479   0.000  eey1/mulw8/complexmul__n0001<0>lut (eey1/mulw8/N4)
     MUXCY:S->O            1   0.435   0.000  eey1/mulw8/complexmul__n0001<0>cy (eey1/mulw8/complexmul__n0001<0>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<1>cy (eey1/mulw8/complexmul__n0001<1>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<2>cy (eey1/mulw8/complexmul__n0001<2>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<3>cy (eey1/mulw8/complexmul__n0001<3>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<4>cy (eey1/mulw8/complexmul__n0001<4>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<5>cy (eey1/mulw8/complexmul__n0001<5>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<6>cy (eey1/mulw8/complexmul__n0001<6>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<7>cy (eey1/mulw8/complexmul__n0001<7>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<8>cy (eey1/mulw8/complexmul__n0001<8>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<9>cy (eey1/mulw8/complexmul__n0001<9>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<10>cy (eey1/mulw8/complexmul__n0001<10>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<11>cy (eey1/mulw8/complexmul__n0001<11>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<12>cy (eey1/mulw8/complexmul__n0001<12>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<13>cy (eey1/mulw8/complexmul__n0001<13>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<14>cy (eey1/mulw8/complexmul__n0001<14>_cyo)
     MUXCY:CI->O           1   0.056   0.000  eey1/mulw8/complexmul__n0001<15>cy (eey1/mulw8/complexmul__n0001<15>_cyo)
     MUXCY:CI->O           1   0.0